4-Way Pseudo Split DRAM Architecture for SDDC
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Solution Overview
Problem
Conventional Single Device Data Correction (SDDC) solutions for DRAM systems require a high number of devices to achieve error detection and correction, especially for higher DRAM densities, which is prohibitively expensive for form factors like stacked memory modules.
Innovation Solution
The 4-way pseudo split DRAM architecture reduces the number of devices needed by logically splitting each DRAM device into four independent slices, sharing clock, command, and data strobe signals, allowing for SDDC configurations with fewer devices while maintaining reliability and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SDDC solutions use more devices to achieve error detection and correction, then reliability is improved, but device complexity and cost increase prohibitively
Solution Approach 1:
The patent divides a single DRAM device into four independent slices (slice 0, slice 1, slice 2, slice 3), each capable of independent operation. This segmentation allows the system to achieve SDDC functionality by selecting specific slices for data storage and error correction rather than requiring multiple complete devices, thereby reducing the total device count while maintaining reliability.
2Quantity of substance
If more devices are used for high-capacity memory channels, then memory capacity is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple slices from the same or different devices into a single memory channel, allowing four memory channels to be formed using fewer devices. By merging slice resources across devices and sharing common infrastructure (packages, interconnects), the system achieves high memory capacity with reduced device count and lower power consumption compared to conventional approaches requiring separate devices for each channel.
Data Source
AI summary
Four-way pseudo split Dynamic Random Access Memory (DRAM) architectures and techniques are described. In one example, a 4-way pseudo split DRAM device includes four slices. In one example, a memory channel includes four pseudo channels, each of the four pseudo channels includes a corresponding slice of each of the plurality of DRAM devices. In one example, each of the four pseudo channels includes one slice from each of the plurality of DRAM devices.