Pseudo SRAM Refresh Timing Control
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Solution Overview
Problem
Conventional pseudo SRAM refresh methods have overly short refresh cycles, leading to ineffective refresh operations and reduced data reliability due to the simultaneous start of new write cycles, which interfere with the completion of refresh operations.
Innovation Solution
A pseudo SRAM refresh method that adjusts the timing of the sub-word line driving signal based on the refresh request signal, allowing for a sufficient time difference between the chip enable signal and the sub-word line driving signal to ensure the refresh operation can be completed effectively, either before or after the next write operation, utilizing a controller with a refresh signal generator and dynamic memory array to manage these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh operation is performed based on the conventional timing method, then the refresh request signal is generated, but the refresh cycle becomes overly short and the refresh operation cannot be effectively performed
Solution Approach 1:
The patent applies preliminary action by determining whether to extend the chip enable signal duration before the refresh operation begins. The controller predicts if the refresh cycle will be insufficient and proactively extends the chip enable signal to ensure the refresh operation has adequate time to complete, preventing data loss before it occurs.
Solution Approach 2:
The patent implements dynamics by making the chip enable signal duration variable rather than fixed. The controller dynamically adjusts the duration of the chip enable signal based on the predicted timing requirements of the refresh operation, allowing the system to adapt the timing parameters in real-time to ensure successful refresh completion.
2Productivity
If the new write cycle starts at the same time as the refresh operation, then the productivity is improved, but the refresh operation is interfered with and data is lost
Solution Approach 1:
The controller performs preliminary prediction to determine if extending the chip enable signal is needed before the conflict occurs. By anticipating the timing conflict between write and refresh operations, the system proactively adjusts the chip enable signal duration to prevent data loss while maintaining write operation continuity.
Solution Approach 2:
The patent uses feedback by having the controller monitor the timing relationship between write cycles and refresh operations. Based on this feedback, the controller dynamically adjusts the chip enable signal duration to ensure refresh operations complete successfully, creating a closed-loop control system that balances productivity and reliability.
3Reliability
If the chip enable signal duration is extended, then the refresh operation can be completed, but the write operation timing is delayed
Solution Approach 1:
The patent applies dynamics by making the chip enable signal duration adjustable rather than fixed. The controller dynamically extends or maintains the original duration based on the predicted timing requirements, allowing the system to optimize between refresh completion and write operation timing on a case-by-case basis.
Solution Approach 2:
The patent implements parameter changes by modifying the duration parameter of the chip enable signal. The controller changes this timing parameter dynamically based on the predicted need for extended refresh time, allowing flexible adjustment of the timing characteristics to resolve the contradiction between refresh completion and write operation timing.
Data Source
AI summary
A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.