Pseudo Static Controls Delay Fault Testing
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Solution Overview
Problem
Existing dynamic core data register circuits are limited in their ability to perform delay fault testing due to the use of a single scan enable signal, which prevents the observation of state transitions and thus restricts overall transition fault test coverage to only static testing.
Innovation Solution
The implementation of separate scan enable signals for clock gating and output control allows for the observation of shift register transitions, enabling delay fault testing by decoupling state transition timing from output control, utilizing a pipeline circuit to generate delayed scan enable signals in accordance with the LOES timing pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single scan enable signal is used for clock gating and output control, then the circuit structure is simple, but delay fault testing cannot be performed and test coverage is limited to static testing only
Solution Approach 1:
The single scan enable signal is segmented into two separate signals: a first scan enable signal for clock gating the shift register and a second scan enable signal for controlling the output circuit. This segmentation allows independent control of clocking and output routing, enabling delay fault testing while maintaining relatively simple circuit structure
Solution Approach 2:
The patent introduces dynamic control of the output circuit based on the second scan enable signal, allowing the output to be routed from either the data register or shift register depending on the test mode. This dynamic routing capability enables the circuit to adapt between static testing and delay fault testing modes
2Reliability
If separate scan enable signals are introduced for clock gating and output control, then delay fault testing is enabled, but the circuit complexity increases
Solution Approach 1:
The first scan enable signal serves multiple functions: it controls the clock gating of the shift register during normal operation and also serves as the launch enable signal for delay fault testing. Similarly, the second scan enable signal controls both the output routing and acts as the capture enable signal. This multi-functionality reduces the need for additional separate signals
3Reliability
If state transitions are observed for delay fault testing, then test coverage increases from 95% to 96.17%, but the timing control mechanism becomes more complex
Solution Approach 1:
The pipeline circuit generates the first scan enable signal in advance based on the second scan enable signal, creating the necessary timing relationship for delay fault testing before the actual transition observation. This preliminary timing setup simplifies the overall control mechanism by pre-establishing the timing sequence
Data Source
AI summary
A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.