Pseudo-triple-port SRAM Bitcell Architecture for Density
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Solution Overview
Problem
Conventional dual-port SRAMs face challenges in achieving high density due to the need for extra access transistors, which reduce the number of bitcells that can be implemented in a given area of die space, limiting their ability to perform simultaneous multiple read or write operations.
Innovation Solution
A pseudo-triple-port SRAM bitcell architecture is introduced, featuring a pair of independent word lines for each access transistor, allowing for single-ended read operations and simultaneous read/write operations without the need for additional access transistors, thereby increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-port SRAM architecture is used to enable simultaneous read/write operations, then operational capability is improved, but device density deteriorates due to extra access transistors
Solution Approach 1:
The patent segments the word line control by providing separate word lines for read operations and write operations. Each bitcell has a read word line and a write word line that can be controlled independently, enabling simultaneous read and write operations without requiring additional access transistors. This segmentation of control signals allows the same physical infrastructure to support multiple operations concurrently.
Solution Approach 2:
The patent introduces dynamic control of word lines where the read word line and write word line can be asserted at different times. The word line controller dynamically selects which word line to assert based on the operation type, enabling flexible simultaneous operations. This dynamic control mechanism allows the system to adapt to different operational modes without hardware changes.
2Adaptability or versatility
If extra access transistors are added for dual-port operation, then simultaneous read/write capability is improved, but area consumption increases reducing density
Solution Approach 1:
The patent makes the existing access transistors universal by enabling them to serve both read and write functions through independent word line control. The same access transistor can be controlled by the read word line for read operations or by the write word line for write operations, eliminating the need for separate read and write access transistors. This multi-functionality approach maintains the same physical hardware while achieving dual-port capability.
3Quantity of substance
If conventional single-port SRAM architecture is used, then device density is maintained, but operational versatility is limited to single read or write operation per word line assertion
Solution Approach 1:
The patent segments the word line control by providing separate word lines for read operations and write operations. Each bitcell has a read word line and a write word line that can be controlled independently, enabling simultaneous read and write operations without requiring additional access transistors. This segmentation of control signals allows the same physical infrastructure to support multiple operations concurrently.
Data Source
AI summary
A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.