Pseudo-Triple-Port SRAM Datapaths for Higher-Density Multi-Port Access
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Solution Overview
Problem
Conventional dual-port SRAMs face challenges in achieving high density due to the need for extra access transistors, which compromises memory density and efficiency in applications requiring simultaneous multiple read or write operations.
Innovation Solution
The implementation of a pseudo-triple-port SRAM design, where each bitcell has two independent word lines for access transistors, allowing for single-ended read operations and differential write operations using a pair of bit lines, thereby increasing memory density and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-port SRAM is used to enable simultaneous multiple read or write operations, then operational capability is improved, but memory density deteriorates due to extra access transistors
Solution Approach 1:
The patent merges the read and write port functionality into a unified dual-port structure where the same pair of access transistors serves both read and write operations. By sharing the bit lines and access transistors between read and write ports, the design eliminates redundant transistors while maintaining the capability for simultaneous read and write operations to different bitcells.
Solution Approach 2:
The access transistors and bit lines are designed to serve multiple functions - they can be used for both read operations and write operations. The control logic dynamically configures the same physical infrastructure to perform different operations based on the operational mode, thereby reducing the total number of transistors needed while maintaining dual-port functionality.
2Quantity of substance
If conventional single-port SRAM is used, then transistor count is minimized, but operational efficiency deteriorates in applications requiring simultaneous multiple operations
Solution Approach 1:
The patent implements dynamic control of the access transistors through independent word line control for read and write operations. The control logic dynamically switches between read and write modes by asserting appropriate control signals, enabling the same hardware infrastructure to adaptively perform different operations based on real-time requirements, thereby improving operational efficiency without increasing transistor count.
Solution Approach 2:
The design enables continuous useful action by allowing overlapping read and write operations to proceed simultaneously in different bitcells. The shared infrastructure is kept continuously utilized through intelligent control signaling, ensuring that the memory system maintains high productivity without idle transistors or bit lines.
Data Source
AI summary
A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.