Pseudo-Triple-Port SRAM Decoding for Higher-Density Read/Write Access
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Solution Overview
Problem
Conventional dual-port SRAMs face challenges in achieving high density due to the need for extra access transistors, which reduces the number of bitcells that can be implemented in a given area of die space, limiting simultaneous read/write operations.
Innovation Solution
A pseudo-triple-port SRAM design is introduced, where each bitcell has a pair of independent word lines to control access transistors for both true and complement bit lines, allowing for simultaneous read operations and increasing density by using a single pair of bit lines and access transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port SRAM is used to enable simultaneous read/write operations, then productivity is improved, but device complexity increases due to extra access transistors
Solution Approach 1:
The patent merges the functionality of multiple port access transistors into a single shared pair of access transistors per bitcell. The shared bit lines are selectively connected to different word lines through timing-controlled switching, allowing dual-port functionality without duplicating access transistor pairs. This reduces device complexity while maintaining simultaneous read/write capability.
Solution Approach 2:
The patent introduces dynamic switching mechanisms that reconfigure the connection between bit lines and word lines based on operation type (read/write) and port selection. The bit line switching network dynamically connects the shared bit lines to appropriate word lines at different times, enabling flexible multi-port access without static duplication of access transistors.
2Productivity
If extra access transistors are added for dual-port functionality, then productivity is improved, but area of die space increases
Solution Approach 1:
The patent combines the access transistor pairs from multiple ports into a single shared pair per bitcell. By using time-division multiplexing and dynamic bit line switching, the same physical access transistors serve multiple ports sequentially, dramatically reducing the area required compared to having separate access transistor pairs for each port.
Solution Approach 2:
The shared access transistors and bit lines are designed to serve multiple functions and multiple ports. The same bit line pair is universally used for both read and write operations across different ports, with selection controlled by timing signals and switching networks, thereby maximizing area utilization.
3Quantity of substance
If single pair of bit lines is used per column, then density is improved, but productivity is limited to single operation per word line assertion
Solution Approach 1:
The patent introduces dynamic switching networks that enable a single bit line pair to be dynamically connected to different word lines at different times within the same assertion period. This temporal multiplexing allows multiple operations to be performed on the same column using the same bit lines, increasing productivity without sacrificing density.
Solution Approach 2:
The patent employs periodic switching of bit line connections during the word line assertion period. The bit lines are periodically connected to different word lines in a controlled sequence, enabling multiple read or write operations to be performed on the same column within a single word line assertion cycle, thereby increasing throughput while maintaining high density.
Data Source
AI summary
A word line decoder for pseudo-triple-port memory is provided that includes a first logic gate for decoding a word line address to a first word line in a word line pair and a first word line clock signal. The decoder further includes a second logic gate for decoding a word line address to a second word line in the word line pair and a second word line clock signal.