Pseudomorphic InGaAs Gate-All-Around Transistors
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Solution Overview
Problem
The challenge in semiconductor technology is to maintain mobility improvements while increasing short channel control in non-planar transistors, particularly in Gate-All-Around transistors, where significant improvements in source to drain leakage are still needed.
Innovation Solution
The solution involves pseudomorphically growing a channel layer over a buffer layer within a shallow trench isolation (STI) structure, forming a multi-layer stack in-situ without exposing the layers to air, which prevents strain and misfit dislocations, and using a cap layer and buffer layer to surround the channel layer, ensuring cleanliness and defect prevention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-planar transistors such as tri-gate, FinFETs, and omega-FETs are used to increase short channel control, then source to drain leakage control is improved, but maintaining mobility improvements becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar to three-dimensional gate structures (tri-gate, FinFETs, omega-FETs, and gate-all-around configurations) to achieve better channel control. This dimensional change allows the gate to surround the channel on multiple surfaces, significantly improving short channel control and reducing source to drain leakage while maintaining manufacturing feasibility through established semiconductor processes.
2Manufacturing precision
If the channel layer is grown pseudomorphically over the buffer layer to maintain lattice matching, then misfit dislocations are prevented, but the channel layer thickness is limited by critical thickness
Solution Approach 1:
The patent employs pseudomorphic growth to maintain lattice matching between the InGaAs channel layer and GaAs buffer layer, preventing misfit dislocations. By controlling the channel layer thickness to remain below the critical thickness, the patent achieves high manufacturing precision while maximizing the usable channel thickness for device performance.
3Reliability
If the multi-layer stack is formed in-situ without exposing to air, then strain and misfit dislocations are prevented, but process complexity increases
Solution Approach 1:
The patent combines multiple layer formation steps (buffer layer, channel layer, cap layer) into a continuous in-situ growth process without air exposure. This merging of steps prevents strain accumulation and misfit dislocations while the patent manages process complexity through integrated semiconductor fabrication techniques.
4Manufacturing precision
If cap layer and buffer layer are used to surround the channel layer, then cleanliness and defect prevention are improved, but manufacturing steps increase
Solution Approach 1:
The patent uses thin film structures (cap layer and buffer layer) to surround and protect the channel layer. These flexible thin films provide defect prevention and maintain cleanliness while being compatible with standard thin film deposition techniques in semiconductor manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances channel electron mobility, reduces defects and contamination, and improves transistor drive capability without increasing lateral area, resulting in a compact and efficient transistor design.
Implementation Method 1
the channel layer is pseudomorphically grown over a buffer layer such that the thickness of the channel layer is smaller than its critical thickness
Data Source
AI summary
A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.