Pseudo-Random Permutation Circuit for Low-Complexity Hardware
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Solution Overview
Problem
Existing pseudo-random permutation generation mechanisms are complex, bulky, and not scalable for systems with strong hardware constraints, requiring a simpler, more compact, and efficient solution.
Innovation Solution
A method and circuit for generating pseudo-random permutation sequences by iteratively generating a chain of numbers from an initial seed using a first function followed by a second function that includes a permutation and bijection, allowing on-the-fly generation of digital codes for reordering values, which is adapted for low-consumption circuits and compressive image acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing pseudo-random permutation generation mechanisms are used, then permutation functionality is achieved, but hardware complexity and bulk increase
Solution Approach 1:
The patent combines the permutation operation and bijection operation into a single integrated function (second function), eliminating the need for separate hardware modules for each operation. This merging reduces hardware complexity while maintaining the complete pseudo-random permutation functionality through iterative application of the combined function.
Solution Approach 2:
The patent creates a universal generator that can produce pseudo-random permutation sequences for different applications (cryptography, imaging, transmissions) using the same core hardware structure. The generator is configurable through seed values and iteration counts, allowing one device to serve multiple purposes without requiring application-specific hardware variants.
2Device complexity
If existing pseudo-random permutation generation mechanisms are used, then permutation functionality is achieved, but hardware size increases
Solution Approach 1:
The patent implements a nested structure where the second function (permutation + bijection) is applied iteratively to the output of the first function, with each iteration nesting within the previous one. This nested approach allows complex permutation sequences to be generated through repeated application of a simple core function, reducing overall hardware size compared to implementing the entire sequence generation in a single complex stage.
Solution Approach 2:
The patent uses dynamic seed values that change with each iteration to generate different permutation sequences on-the-fly. Instead of storing multiple static permutation tables in hardware, the system dynamically generates sequences by iterating the same function with updated seed values, significantly reducing hardware size while maintaining functionality.
3Adaptability or versatility
If existing pseudo-random permutation generation mechanisms are used, then permutation functionality is achieved, but scalability is limited
Solution Approach 1:
The patent enables scalability by allowing configuration through parameter changes rather than hardware redesign. The number of iterations, seed values, and input/output set sizes can be adjusted to scale the permutation generation to different application requirements while using the same underlying hardware structure, making the system adaptable to various hardware constraints.
4Reliability
If complex permutation generation mechanisms are used, then permutation quality is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic iteration of the second function applied to successive outputs of the first function to generate high-quality pseudo-random sequences. This periodic application of a simple, low-power function achieves the same permutation quality as complex one-time operations but with significantly lower power consumption, as the same hardware circuit is reused multiple times rather than employing a single complex high-power circuit.
Data Source
AI summary
The present description concerns a method of generation of a sequence of pseudo-random digital codes enabling to perform a permutation (3) of a first set of values (V) into a second set of values (Vp) based on said digital codes (CPos) representative of positions (j) of values (Vi) of the first set in the second set, including the steps of: generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number (W0) by application of a first function (24,26) from a seed number to the next seed number; applying a second function to each seed number of the chain to obtain each position code (CPos(j)), the second function including at least one permutation (PERM) followed by a bijection (BIJ).