Pseudo-Random Sequence Generation Using Simplified LFSR Logic
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Solution Overview
Problem
The generation of pseudo-random sequences in communication systems, such as those used in 3GPP LTE or NR, often results in increased memory and processor resource usage, affecting device performance due to the complexity of existing methods.
Innovation Solution
A method involving simple logic operations like AND and XOR on M bit values of a first sequence to generate an (A+m)th bit value, optimizing resource usage and improving performance by reducing storage space and processor requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Gold sequence generation method is used, then pseudo-random sequence can be generated with good randomness, but memory volume and execution time increase with sequence length
Solution Approach 1:
The patent segments the sequence generation process into two independent linear feedback shift registers (LFSRs) instead of using a single complex Gold sequence generator. Each LFSR generates a simpler sequence, and their combination produces the final pseudo-random sequence. This segmentation reduces the memory requirements and computational complexity while maintaining the desired randomness properties.
Solution Approach 2:
The patent changes the generation parameters from traditional Gold sequence parameters to simplified LFSR parameters. By using specific primitive polynomials and initial states for the two LFSRs, and applying bitwise XOR operation, the system achieves equivalent or superior randomness with reduced memory volume and execution time.
2Reliability
If sequence length is increased to meet communication requirements, then coverage and reliability improve, but occupied memory volume and execution time increase
Solution Approach 1:
The patent enables continuous generation of pseudo-random sequences through the continuous operation of two LFSRs. The linear feedback mechanism allows each register to continuously produce new bits without requiring storage of previous sequences, enabling unlimited sequence length generation with constant memory usage and linear execution time growth.
3Reliability
If complex generation algorithm is used to ensure sequence properties, then randomness and functionality are maintained, but processor resources and operation speed are affected
Solution Approach 1:
The patent replaces complex mechanical/computational operations with simple bitwise XOR operation between two LFSR outputs. This substitution dramatically reduces processor resource requirements and increases operation speed, as bitwise XOR is a fundamental CPU operation that can be executed extremely quickly compared to complex polynomial calculations or memory-intensive algorithms.
Data Source
AI summary
A method and an apparatus for generating a pseudo-random sequence, an electronic device, and a computer-readable storage medium. The method for generating a pseudo-random sequence comprises: performing an AND operation and an XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence; where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0 (100); and determining, according to the (A+m)th bit value of the first sequence, an mth bit value of the pseudo-random sequence (101).