pSLC Cache Segmentation for NAND Error Correction
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Solution Overview
Problem
Multibit NAND media, such as TLC NAND media, is prone to read errors and requires more robust error correction mechanisms, leading to slower performance and reduced input/output operations per second (IOPs) compared to SLC and MLC NAND media, and this issue is expected to worsen with next-generation storage technologies like QLC NAND media.
Innovation Solution
Implementing a pseudo-SLC (pSLC) caching technique in SSDs, where a portion of multibit NAND media operates as a pSLC cache and a multibit NAND media storage area, with a memory controller that writes data to the pSLC cache, transfers data to the NAND media, and manages ECC error correction, marking bad blocks and optimizing storage capacity to improve performance and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multibit NAND media (TLC/QLC) is used to increase storage capacity, then storage density is improved, but read error rate increases and requires more robust error correction
Solution Approach 1:
The patent divides the NAND media into multiple channels and further segments data into units that can be independently managed. By organizing media into channels and handling data in manageable units, the system can apply error correction selectively and efficiently to affected segments without processing entire storage arrays, thus maintaining reliability while supporting high-capacity multibit media.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the host and NAND media. This buffer temporarily stores data during transfer operations, allowing the system to manage error correction and data integrity checks without directly impacting the high-capacity multibit media performance. The buffer acts as a mediator that decouples the high-capacity storage from the error-prone transmission paths.
2Reliability
If robust error correction mechanisms (QSBC) are implemented to handle read errors, then error correction capability is improved, but processing time increases significantly
Solution Approach 1:
The patent implements error correction on a selective basis rather than applying robust correction mechanisms to all data uniformly. By using LDPC codes for standard cases and reserving QSBC for exceptional cases where LDPC fails, the system applies error correction partially and proportionally to the actual error conditions encountered, minimizing processing time while maintaining adequate correction capability.
Solution Approach 2:
The patent changes the error correction parameter strategy by implementing a tiered approach: using lighter LDPC correction for routine operations and switching to heavier QSBC correction only when necessary. This parameter change in correction intensity based on actual error conditions allows the system to maintain reliability while avoiding the constant time penalty of always using the most robust correction mechanism.
3Quantity of substance
If multibit NAND media is used to increase storage density, then capacity is improved, but input/output operations per second (IOPs) decrease
Solution Approach 1:
The patent segments the NAND media into multiple independent channels, allowing parallel I/O operations across channels. This segmentation enables the system to maintain high IOPs by distributing operations across multiple channels simultaneously, offsetting the inherent slowness of individual multibit NAND cells while preserving the high storage density benefits.
Solution Approach 2:
The buffer memory serves multiple functions: it acts as a temporary storage area during data transfers, a staging area for error correction operations, and a mechanism for coordinating between the host and multibit NAND media. This multi-functionality allows the system to maintain high productivity by using the buffer for various optimization tasks rather than requiring dedicated hardware for each function.
Data Source
AI summary
A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.