Power Supply Noise Sensor With Independent Clock Delay Capture
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Solution Overview
Problem
Existing power supply noise (PSN) sensors are cumbersome, rely heavily on system clocks, and require extensive calibration, making them impractical for in-field use due to process variation and temperature imbalance, and lack portability across different product designs.
Innovation Solution
A power supply noise sensor design utilizing a dedicated clock, half-cycle delay circuit, and series of flops in a delay capture circuit, powered by both clean and noisy power sources, with a clock generation circuit isolated to minimize electromagnetic interference, allowing for independent clock operation and reduced size, and using homogeneous gates to minimize process and temperature variation impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing PSN sensors use system clock as reference, then measurement can be performed, but measurement accuracy deteriorates due to clock noise and process variation
Solution Approach 1:
The patent extracts the clock reference function from the system clock and creates a dedicated local clock generator within the PSN sensor. This separation allows the sensor to have its own independent timing reference that is not affected by system clock noise or process variations, thereby improving measurement accuracy and reliability.
Solution Approach 2:
The patent introduces a dedicated clock generator as an intermediary component between the power supply being measured and the measurement logic. This intermediary provides a stable, isolated timing reference that mediates the measurement process, preventing direct coupling between system clock variations and measurement accuracy.
2Measurement precision
If PSN sensor requires individual calibration for each sensor cell, then measurement accuracy can be maintained, but device complexity and calibration time increase significantly
Solution Approach 1:
The patent employs homogeneous gates throughout the sensor design, ensuring uniform response characteristics across all sensor cells. This homogeneity allows a single calibration sequence to effectively calibrate all cells simultaneously, eliminating the need for individual calibration while maintaining measurement accuracy.
Solution Approach 2:
The patent creates a universal calibration sequence that can calibrate all PSN sensor cells simultaneously. This multi-functional calibration approach replaces the need for individual calibration procedures, reducing device complexity and calibration time while maintaining measurement precision across all sensor cells.
3Measurement precision
If PSN sensor design is highly optimized for specific process corners, then measurement accuracy improves, but portability to other products deteriorates
Solution Approach 1:
The patent designs the sensor with parameters that can be adjusted through a single calibration sequence rather than being fixed for specific process corners. This allows the sensor to adapt to different process variations and technology nodes while maintaining measurement accuracy, thereby improving portability across different product designs.
Data Source
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AI summary
An integrated circuit includes a clock generator to generate a first clock signal, a delay circuit to generate a second clock signal as a delayed version of the first clock signal, and a plurality of series-connected delay elements having a plurality of outputs, wherein each output from an initial output to a last output is configured to provide the second clock signal delayed by an increasing number of series-connected delay elements. The circuit includes a plurality of flip-flops, wherein a first input of each flip flop is coupled to receive the first clock signal and a second input of each flip flop from an initial flip-flop to a last flip-flop is coupled to receive a corresponding output of the series-connected delay elements from the initial output to the last output, respectively. The circuit includes a plurality of sticky flops, each corresponding to a flip-flop of the plurality of flip-flops.