Pseudo-Static RAM Column Select Signal Length Control
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Solution Overview
Problem
Conventional pseudo-static random-access memory (pSRAM) systems experience unnecessary power consumption and prolonged operation times due to the generation of redundant column select signals and the need for a fixed-length column select signal, which is longer than required for data input/output operations.
Innovation Solution
The proposed solution involves a pseudo-static random-access memory system that dynamically adjusts the length of the column select signal based on the number of read data, utilizing a memory array, input/output circuit, count-and-command decoder, burst-length counter, row-and-column control circuit, delay control circuit, and input/output control circuit to calculate a burst length suitable for the read data and synchronize the column select signal with this burst length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed-length column select signal is generated to ensure complete data output, then data reliability is improved, but unnecessary power consumption increases due to redundant pulses
Solution Approach 1:
The patent applies dynamics by making the column select signal length variable rather than fixed. The burst length counter dynamically adjusts the number of column select pulses based on the actual data transfer requirements, allowing the signal duration to adapt to different read operation scenarios and eliminate redundant pulses.
Solution Approach 2:
The patent changes the parameter of column select signal length from a fixed value to a variable value determined by the burst length. This parameter change enables the system to optimize power consumption by matching the signal duration exactly to the data output requirements without waste.
2Device complexity
If a fixed-length column select signal is used to simplify control logic, then device complexity is reduced, but operation time increases due to inability to terminate early
Solution Approach 1:
The patent introduces dynamic control through the burst length counter and delay control circuit, which adjust the column select signal duration based on actual data transfer completion. This dynamic approach reduces operation time by allowing early termination while maintaining manageable control logic through modular circuit design.
3Loss of energy
If the column select signal length is reduced to match actual data output time, then power consumption decreases, but data reliability may be compromised if signal terminates too early
Solution Approach 1:
The patent implements feedback through the delay control circuit and burst length counter, which monitor the data output process and adjust the column select signal duration accordingly. This feedback mechanism ensures the signal persists exactly as long as needed for complete data transfer, preventing both early termination and excessive duration.
4Reliability
If redundant column select pulses are generated to ensure complete data read, then data completeness is improved, but processing speed decreases due to extended operation duration
Solution Approach 1:
The patent changes the column select signal length parameter from fixed to variable, optimizing it to match exactly the time required for data output. This eliminates redundant pulses that extend operation duration, thereby improving processing speed while maintaining data read completeness through the burst length control mechanism.
Data Source
AI summary
A pseudo-static random-access memory is provided. A count-and-command decoder starts counting a clock signal when an internal enable signal changes from a disable state to an enable state, and outputs a column address strobe signal at a first level when the count reaches a first clock amount. During a period starting from when the column address strobe signal changes from a second level to the first level to when the internal enable signal changes from the enable state to the disable state, a burst-length counter counts the clock signal to provide a burst length accordingly. A delay control circuit outputs a first confirmation signal at the first level to a row-and-column control circuit, such that a length of a column select signal is equal to the burst length.