PSRAM In-Memory Logic Using Sub-Sense Amplifiers
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Solution Overview
Problem
Traditional von-Neumann computing architectures and application-specific processing-in-memory (PIM) designs face limitations in memory bandwidth, energy efficiency, and programmability, with PIM platforms struggling to keep pace with evolving software algorithms due to high latency and intermediate data write-back in bit-serial algorithms.
Innovation Solution
A programmable processing-in-static random-access memory (PSRAM) accelerator design that performs 2- and 3-input Boolean logic operations in a single cycle using a layered subarray of volatile memory with sub-sense amplifiers and multiplexers, eliminating redundant write-back operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If application-specific processing-in-memory (PIM) designs are used to improve memory bandwidth and energy efficiency, then performance is improved, but programmability and flexibility deteriorate as they are limited to one specific type of algorithm or application domain
Solution Approach 1:
The patent implements a PIM architecture that can perform multiple logic operations (AND, OR, NAND, NOR, XOR, XNOR) and support both bit-parallel and bit-serial algorithms through a unified design. The sense amplifiers are configured to execute different Boolean functions by selecting appropriate reference voltages, enabling a single memory device to serve multiple algorithmic purposes without sacrificing performance or programmability
2Adaptability or versatility
If bit-serial algorithms are used to improve programmability and flexibility, then adaptability is improved, but latency increases and intermediate data write-back operations are required
Solution Approach 1:
The patent employs dynamic reference voltage selection to switch between different logic operations and algorithmic modes. By dynamically adjusting the reference voltage levels applied to the sense amplifiers, the system can adapt between bit-parallel and bit-serial operations, achieving both high programmability and low latency without requiring intermediate data write-back
Solution Approach 2:
The invention changes the operational parameters of the sense amplifiers by varying reference voltages to perform different logic functions. This parameter-based control enables the same hardware to execute multiple algorithms with different latency requirements, eliminating the need for data write-back while maintaining flexibility
3Adaptability or versatility
If multiple computing cycles are needed for basic in-memory Boolean logic functions to improve programmability, then adaptability is improved, but the number of operations per second decreases
Solution Approach 1:
The patent pre-configures multiple sense amplifiers within the memory device, each capable of performing different logic operations simultaneously. By having these computational units ready in advance and able to operate in parallel, the system achieves high operations per second while maintaining programmability through selective activation of different amplifier configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PSRAM accelerator achieves high throughput, energy efficiency, and programmability, supporting various applications like parallel vector operations, neural networks, and data encryption, with a peak throughput of 1.2 tera operations per second and energy efficiency of 34.98 TOPs/W, outperforming prior designs in speed and latency.
Implementation Method 1
comparing, with a set of sub-sense amplifiers, an analog voltage of a read bitline of the volatile memory to a set of corresponding voltage references, each voltage reference corresponding to a digital logic operation
Data Source
AI summary
A system for in-memory computing comprises a volatile memory comprising at least a first layered subarray, wherein each subarray comprises a plurality of memory cells, and a plurality of sub-sense amplifiers connected to a read bitline of the first subarray of the memory, configured to compare a measured voltage of the read bitline to at least one threshold and provide at least one binary output corresponding to a logic operation based on whether the voltage of the read bitline is above or below the threshold. A method for in-memory computing is also disclosed.