Pseudo Static Random Access Memory Read Latency Stabilization
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Solution Overview
Problem
In pseudo static random access memory (pSRAM) systems, self-refresh collisions lead to inconsistent read latency, causing bus conflicts and increased current consumption due to asynchronous self-refresh operations among stacked memory chips, which can result in unexpected voltage drops and bus conflicts even when using the same bus for read/write data strobe signals.
Innovation Solution
Implementing a pSRAM system where the read/write data strobe signals are kept at a constant level during read latency, setting it to a fixed period greater than initial latency, ensuring self-refresh completion regardless of self-refresh collisions, and using the same bus for all memory chips to prevent bus conflicts, even among chips with different operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips perform self-refresh operations asynchronously during burst read/write, then memory density is increased through stacking, but bus conflict occurs and current consumption increases
Solution Approach 1:
The patent applies preliminary action by setting the read latency period to be greater than the initial latency required for self-refresh completion. This ensures that self-refresh operations are completed before data output begins, preventing bus conflicts caused by asynchronous self-refresh collisions during the data transmission phase.
Solution Approach 2:
The patent implements dynamics by making the RWDS signal level changeable during the latency period. The signal transitions from a first level during self-refresh to a second level during data output, allowing the system to adapt to different operational phases and prevent bus conflicts while maintaining efficient data transmission.
2Reliability
If read latency is adjusted based on self-refresh collision detection, then data integrity is maintained, but read latency becomes inconstant
Solution Approach 1:
The patent resolves this contradiction by performing self-refresh operations during the extended latency period before data output. By completing self-refresh in advance and using signal level changes to indicate completion, the system maintains constant read latency while ensuring data integrity through proper self-refresh execution.
Solution Approach 2:
The RWDS signal level acts as an intermediary indicator between the memory chip's internal self-refresh status and the external data transmission state. This mediator allows the system to coordinate asynchronous self-refresh operations with synchronous data output, maintaining both data integrity and constant latency.
3Device complexity
If multiple memory chips share the same bus for RWDS signals, then device complexity is reduced, but bus conflict occurs due to asynchronous operations
Solution Approach 1:
The patent resolves the bus conflict issue by ensuring self-refresh operations complete before data output begins. The extended latency period serves as a preliminary action phase where all chips synchronize their self-refresh completion, allowing subsequent data transmission on the shared bus to proceed without conflicts.
Solution Approach 2:
The dynamic RWDS signal level provides a coordination mechanism for multiple chips sharing the same bus. When chips are not outputting data, the signal remains at the first level, preventing bus conflicts. When data output begins, the transition to the second level indicates safe bus usage, enabling simple shared bus architecture without reliability issues.
Data Source
AI summary
A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.