Pseudo Static Random Access Memory Write Mode Transition
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Solution Overview
Problem
Current pseudo static random access memory (PSRAM) has a limited refresh time between write operations, leading to decreased data retention and increased power consumption due to short refresh cycles, and complex control logic that raises costs and chip size.
Innovation Solution
A PSRAM system with a controller that includes counters, a comparer, and an address strobe clock generator, allowing the write operation to transition from asynchronous to synchronous mode, adjusting the built-in clock signal to match the reference clock signal, thereby reducing write operation time and extending refresh time without increasing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh cycle is shortened to avoid errors, then data retention reliability is improved, but standby current increases and power consumption increases
Solution Approach 1:
The patent applies dynamics by making the refresh cycle variable rather than fixed. The refresh controller dynamically adjusts the refresh timing based on whether the memory device is in read mode or write mode. In write mode, the refresh cycle is extended by utilizing the write operation time window, while in read mode, normal refresh timing is maintained. This dynamic adaptation resolves the contradiction by optimizing power consumption for each operational context while ensuring data retention reliability is maintained through appropriate refresh scheduling.
2Reliability
If a more complex control is applied to the refresh action and refresh cycle, then data retention reliability is improved, but control logic circuit complexity increases and chip size increases
Solution Approach 1:
The patent applies universality by designing the refresh controller to perform multiple functions using the same control logic. The refresh controller not only manages regular refresh operations but also intelligently utilizes write operation time windows to perform refresh actions. This multi-functionality eliminates the need for separate complex control circuits, as the same refresh control mechanism handles both traditional refresh and write-time refresh operations, thereby maintaining data retention reliability without increasing control logic circuit complexity or chip size.
3Productivity
If the time for write operation is reduced, then productivity is improved, but refresh time available decreases and data retention reliability worsens
Solution Approach 1:
The patent applies continuity of useful action by ensuring that refresh operations continue uninterrupted during write operations. Instead of treating write operations as time that must be subtracted from refresh scheduling, the system performs refresh actions concurrently with write operations by utilizing the write time window. This continuous utilization of time resources allows write operations to proceed at full speed while refresh actions simultaneously maintain data retention, eliminating the trade-off between productivity and reliability.
Data Source
AI summary
In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal.