PSRAM Write Timing Adjustment for Refresh Conflict Resolution
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Solution Overview
Problem
Pseudo static random access memory requires periodic refresh operations that conflict with write operations, leading to increased power consumption due to shortened refresh periods.
Innovation Solution
A method and system that adjust internal clock signals to avoid conflicts between refresh and write operations by delaying internal clock signals when a refresh conflict is detected, allowing for simultaneous execution of both operations without shortening the refresh period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh period is shortened to avoid conflict with write operations, then data reliability is maintained, but power consumption increases due to increased current during standby
Solution Approach 1:
The patent dynamically adjusts the timing of write operations based on the refresh cycle. The write operation timing is made flexible by introducing a delay mechanism that adapts to the refresh schedule, allowing the system to optimize between maintaining data reliability and reducing power consumption during standby periods
Solution Approach 2:
The patent changes the timing parameter of write operations by delaying them until after the refresh operation completes. This parameter adjustment allows the refresh period to remain unchanged while avoiding conflicts, thereby maintaining data reliability without increasing power consumption
2Use of energy by moving object
If the refresh operation is prioritized over write operation, then power consumption is reduced by maintaining normal refresh period, but write operation timing is delayed
Solution Approach 1:
The patent performs preliminary detection of refresh operation timing before initiating write operations. By checking whether a refresh operation is currently executing and predicting upcoming refresh cycles, the system can proactively schedule write operations to avoid conflicts, thereby reducing power consumption while minimizing timing delays through advance planning
Data Source
AI summary
A pseudo static random access memory and a method for writing data thereof are provided. In the method, a basic clock signal having a basic cycle is provided. A chip enable signal is enabled to perform a write operation and write data is received during an enabled time interval of the chip enable signal. A plurality of internal clock signals is generated sequentially at intervals of the basic cycle according to a write command enable signal. A refresh conflict signal is received and it is determined whether the refresh conflict signal is enabled. When the refresh conflict signal is enabled, the internal clock signals are delayed, and the write data is written to a selected sensing amplifier according to the delayed internal clock signals.