Perpendicular STT-MRAM Cell with In-Stack Thermal Barriers
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Solution Overview
Problem
Existing MRAM memory cell designs face challenges in achieving high bit density and endurance due to high write current requirements and low write margin, which limit memory density and reliability.
Innovation Solution
A perpendicular spin transfer torque MRAM memory cell with in-stack thermal barriers is proposed, featuring a magnetic tunnel junction stack with a pinned layer, a free layer, a tunnel barrier, and multi-layer thermal barriers that maintain self-induced heat while minimizing electrical resistance, allowing for lower write currents and increased write margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MRAM memory cell designs are used, then the basic memory function is achieved, but high write current requirements and low write margin limit memory density and reliability
Solution Approach 1:
The patent changes the magnetization switching mechanism by utilizing spin transfer torque with perpendicular magnetization orientation. This parameter change in the magnetic configuration enables lower write currents and higher write margins compared to conventional in-plane magnetization MRAM designs, directly resolving the contradiction between reliability and energy consumption
Solution Approach 2:
The patent employs composite magnetic tunnel junction structures with multiple layers including pinned layers, free layers, and barrier layers with specific material compositions. These composite materials enable enhanced spin transfer torque efficiency and thermal management, allowing lower write currents while maintaining high reliability and endurance
2Reliability
If high write current is used to ensure reliable switching, then magnetization switching is achieved, but bit density decreases due to larger transistor requirements
Solution Approach 1:
By changing to perpendicular magnetization switching with spin transfer torque, the patent achieves higher write margins with lower current requirements. This parameter change allows smaller transistor sizes while maintaining reliable switching, thereby increasing bit density without sacrificing write margin
Solution Approach 2:
The patent replaces conventional magnetic field-based switching mechanisms with spin transfer torque switching. This substitution enables more efficient magnetization reversal with lower current requirements, reducing the transistor size needed while maintaining high write margins for reliable operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher bit density and improved endurance and reliability by reducing the switching current and increasing the write margin, allowing for more efficient and reliable memory operations with smaller transistors and lower power consumption.
Implementation Method 1
The thermal barriers have high enough thermal resistivity to maintain the self-induced heat generated in the memory cell
Implementation Method 2
A bit of data is written to a memory cell by changing the direction of magnetization of a magnetic element within the memory cell... perpendicular spin transfer torque MRAM memory cell
Implementation Method 3
a tunnel barrier between the pinned layer and the free layer... low enough electrical resistivity to not materially change the electrical resistance of the memory cell
Data Source
AI summary
A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a tunnel barrier between the pinned layer and the free layer, a cap layer above the free layer and one or more in-stack multi-layer thermal barrier layers having multiple internal interfaces between materials. The thermal barrier layers have high enough thermal resistivity to maintain the heat generated in the memory cell and low enough electrical resistivity to not materially change the electrical resistance of the memory cell. One embodiment further includes a thermal barrier liner surrounding the free layer, pinned layer, tunnel barrier and cap layer.