PTC Circuit Layout for Faster Overcurrent Trip Response

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Solution Overview

Problem

Conventional PTC circuit protection devices have a time to trip of several seconds, which is not sufficient to rapidly react to overcurrent conditions, leading to potential damage to protected components due to electrical arcing.

Innovation Solution

The proposed PTC circuit protection device incorporates a dielectric substrate layer with high resistance layers and a PTC layer, where the PTC layer is strategically positioned under a gap between the high resistance layers, and a mask layer covers the PTC layer and high resistance layers, reducing the quantity of PTC material and enhancing thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional PTC material is used in sufficient quantity to ensure high electrical resistance, then the device maintains reliable circuit protection, but the time to trip increases to several seconds due to thermal mass

Engineering Contradiction:
Improveelectrical resistanceVSAvoidtime to trip
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The PTC layer is segmented into two distinct regions: a first region with high PTC material concentration for maintaining electrical resistance, and a second region with low PTC material concentration for rapid heating and tripping. This spatial segmentation allows the device to simultaneously achieve both high reliability and fast response time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the PTC layer are assigned different material concentrations tailored to their specific functions: the first region (near terminals) uses high concentration for resistance stability, while the second region (central area) uses low concentration for rapid thermal response. This local quality differentiation resolves the contradiction between reliability and speed.

Inventive Principle:
Principle #3Local quality

2Reliability

If a large quantity of PTC material is used to ensure adequate electrical resistance, then circuit protection reliability is maintained, but the device complexity and material cost increase

Engineering Contradiction:
Improveelectrical resistanceVSAvoidPTC material quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The PTC layer is divided into functional zones with different material concentrations, eliminating the need to use high quantities of PTC material throughout the entire layer. Only the first region requires high concentration for resistance, while the second region uses minimal material for timing control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The PTC material concentration parameter is varied spatially across the layer, creating a gradient or stepped distribution where concentration decreases from the first region to the second region. This parameter change allows reduced overall material quantity while maintaining necessary electrical resistance.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If uniform PTC material distribution is used throughout the layer, then manufacturing is simplified, but the time to trip is excessive due to uniform thermal mass

Engineering Contradiction:
Improvematerial distribution uniformityVSAvoidtime to trip
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The manufacturing process is segmented into stages that deposit PTC material with different concentrations in different regions. This controlled non-uniform deposition achieves the desired functional gradient while remaining manufacturable through established techniques.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The manufacturing process is designed to create local quality variations in PTC material concentration, with specific deposition parameters tailored for each region. This approach maintains manufacturing feasibility while achieving the non-uniform distribution necessary for fast tripping.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves a significantly faster time to trip, ranging from 10^-1 milliseconds to 10^3 milliseconds, while maintaining high electrical resistance, thus effectively protecting circuit components from overcurrent damage.

Implementation Method 1

PTC materials exhibit a relatively low electrical resistance within a normal operating temperature range. However, when the temperature of a PTC material exceeds the normal operating temperature range and reaches a 'trip temperature,' such as may result from excessive current flowing through the PTC material, the resistance of the PTC material increases sharply.

Methodology Applied
Scientific EffectPositive temperature coefficient effect: Thermistor

Implementation Method 2

when excessive current flowing through the PTC material, the resistance of the PTC material increases sharply. This increase in resistance mitigates or arrests the flow of current through the PTC element.

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS20250183655A1Rapid reaction PTC circuit protection device
Publication Date: 2025.06.05 LITTELFUSE INC
  • US20250183655A1 patent drawing
  • US20250183655A1 patent drawing
  • US20250183655A1 patent drawing

AI summary

A positive temperature coefficient (PTC) circuit protection device including a dielectric substrate layer, first and second high resistance layers disposed on a top surface of the substrate layer in a spaced apart relationship to define a gap therebetween, a PTC layer disposed on the top surface of the substrate layer in the gap and in contact with the first and second high resistance layers, a mask layer covering a top surface of the PTC layer and portions of top surfaces of the first and second high resistance layers, an electrically conductive first terminal covering a first longitudinal end of the substrate layer and an outermost end of the first high resistance layer distal from the PTC layer, and an electrically conductive second terminal covering a second longitudinal end of the substrate layer and an outermost end of the second high resistance layer distal from the PTC layer.