Page Table Caching Memory Object Locking
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Solution Overview
Problem
High-performance computing and data center processing systems face increased address translation latency due to large virtual memory regions with irregular access patterns, exceeding the capacity of processor address translation caches, leading to poor application performance.
Innovation Solution
The implementation of page table caching memory objects (PTCMs) where page tables are copied and locked in processor caches, preventing eviction and reducing page table walker accesses, thereby enhancing memory access performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large virtual memory regions with irregular access patterns are used, then memory capacity is increased, but address translation latency increases due to exceeding TLB capacity
Solution Approach 1:
The patent segments the address translation function by introducing a dedicated page table cache structure that separates frequently accessed page table entries from main memory. This segmentation allows the system to handle large virtual memory regions by caching only the critical translation entries in the dedicated cache, thereby reducing address translation latency without sacrificing memory capacity.
Solution Approach 2:
The patent implements preliminary action by pre-loading page table entries into the dedicated page table cache before they are needed for address translation. The cache is populated in advance with translation entries that are likely to be accessed, so when address translation is required, the system can retrieve translations from the cache rather than waiting for main memory access, thus reducing latency.
2Speed
If processor address translation caches (TLBs) are used, then address translation speed is improved, but capacity is insufficient for large virtual memory regions
Solution Approach 1:
The patent extends the address translation cache concept into a new dimension by creating a dedicated page table cache structure that exists separately from the traditional TLB hierarchy. This dedicated cache provides an additional layer of capacity beyond the standard TLBs, allowing the system to maintain fast address translation speeds while accommodating large virtual memory regions that exceed traditional cache capacities.
Solution Approach 2:
The patent uses copying by duplicating relevant page table entries from main memory into the dedicated page table cache. This copying mechanism allows the system to have multiple copies of critical translation entries - one in main memory and another in the dedicated cache - enabling fast retrieval without sacrificing the completeness of the address translation information needed for large virtual memory regions.
3Reliability
If page table walker accesses to non-cached memory are performed, then complete address translation is achieved, but memory access performance decreases
Solution Approach 1:
The patent applies preliminary action by pre-populating the dedicated page table cache with translation entries before memory access operations occur. This ensures that when address translation is needed, the translations are already available in the cache, eliminating the need for page table walker accesses to non-cached memory and maintaining both completeness and performance.
Solution Approach 2:
The dedicated page table cache acts as an intermediary between the address translation logic and main memory. Instead of directly accessing main memory for every translation request, the system first checks this intermediate cache structure, which holds frequently accessed translation entries. This intermediary layer ensures complete address translation while avoiding slow main memory accesses, thus maintaining both reliability and productivity.
Data Source
AI summary
A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.