Page Table Entry Maintenance via Walker-Readable Coherence States
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Processor-based devices face performance issues due to cache contention and memory read operations when the translation lookaside buffer (TLB) is too small to hold page table entries (PTEs), especially in systems with multiple processing elements accessing shared coherence granules, leading to inefficiencies in virtual-to-physical address translation.
Innovation Solution
Implementing two new coherence states, walker-readable (W) and modified walker accessible (Mw), to manage page table entry maintenance, allowing HTWs to read from W state granules while disallowing writes and non-HTW reads, and enabling SP-PTE field store instructions to update SP-PTE fields without additional bus requests, thus optimizing cache coherence and reducing memory reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the TLB is made smaller to reduce its size, then device complexity is reduced, but the frequency of memory read operations increases because PTEs cannot be cached effectively
Solution Approach 1:
The patent segments the coherence granule into two distinct parts: SP-PTE fields (software-specific fields) and non-SP-PTE fields (standard PTE fields). This segmentation allows selective invalidation of only the SP-PTE fields when software modifies them, while preserving the non-SP-PTE fields in the cache. This resolves the contradiction by enabling the TLB to maintain PTEs for fast translation while separately handling software modifications without requiring full cache invalidation.
Solution Approach 2:
The patent applies local quality by creating a specialized coherence state (modified walker-accessible or Mw state) that applies specifically to granules with modified SP-PTE fields. In this state, HTWs can still read the non-SP-PTE fields for address translation, while software can write to SP-PTE fields. This localized approach allows the system to maintain translation performance while accommodating software modifications, resolving the throughput penalty that would otherwise result from smaller TLBs.
2Adaptability or versatility
If software frequently modifies SP-PTE fields, then page table maintenance flexibility is improved, but cache contention and memory read operations increase due to PTE invalidation
Solution Approach 1:
The patent segments the PTE into SP-PTE fields and non-SP-PTE fields, allowing independent handling of each. When software modifies SP-PTE fields, only those specific fields are invalidated and updated, while the non-SP-PTE fields remain valid in the cache for continued address translation. This segmentation enables frequent software modifications without causing full PTE invalidation, thus maintaining translation performance while providing page table maintenance flexibility.
Solution Approach 2:
The patent introduces an intermediary coherence state (Mw state) that acts as a mediator between software modifications and HTW operations. This intermediate state allows software to modify SP-PTE fields while simultaneously allowing HTWs to read non-SP-PTE fields for address translation. The Mw state serves as a buffer that reconciles the conflicting requirements of software flexibility and translation performance, preventing cache contention and unnecessary memory reads.
3Productivity
If multiple PEs access the same coherence granule simultaneously, then system resource utilization is improved, but cache contention increases leading to more memory read operations
Solution Approach 1:
The patent segments the coherence granule into SP-PTE and non-SP-PTE fields, enabling fine-grained coherence management. When multiple PEs access the same granule, the system can allow simultaneous reads of non-SP-PTE fields by multiple HTWs while restricting writes to SP-PTE fields. This segmentation reduces cache contention compared to traditional all-or-nothing coherence models, allowing better resource utilization while managing coherence complexity through field-level control.
Solution Approach 2:
The patent applies local quality by creating a specialized coherence state (Mw) that applies specifically to granules with modified SP-PTE fields. In this state, the granule has different access permissions for different field types: HTWs can read non-SP-PTE fields while software can write SP-PTE fields. This localized coherence management allows multiple PEs to access the same granule simultaneously with appropriate permissions, improving resource utilization while maintaining coherence through targeted control rather than system-wide invalidation.
4Reliability
If PTEs are invalidated from cache upon SP-PTE field modification, then data consistency is improved, but the number of memory read operations increases
Solution Approach 1:
The patent segments the PTE into SP-PTE fields and non-SP-PTE fields, enabling selective invalidation. When software modifies SP-PTE fields, only the SP-PTE fields are invalidated and marked for update, while the non-SP-PTE fields remain valid in the cache. This segmentation maintains data consistency for the modified fields while preserving translation performance by keeping unchanged fields cached, thus resolving the contradiction between consistency and throughput.
Solution Approach 2:
The patent implements a copying mechanism where the modified SP-PTE fields are copied back to system memory when the granule is evicted from the cache (in the Mw state). This copying approach ensures that consistency is maintained by eventually synchronizing modifications to memory, while allowing the cache to retain valid non-SP-PTE fields during the modification period. This resolves the contradiction by maintaining consistency through selective copying rather than through frequent full invalidation and re-fetching of PTEs.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Facilitating page table entry (PTE) maintenance in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) configured to support two new coherence states: walker-readable (W) and modified walker accessible (MW). The W coherence state indicates that read access to a corresponding coherence granule by hardware table walkers (HTWs) is permitted, but all write operations and all read operations by non-HTW agents are disallowed. The MW coherence state indicates that cached copies of the coherence granule visible only to HTWs may exist in other caches. In some embodiments, each PE is also configured to support a special page table entry (SP-PTE) field store instruction for modifying SP-PTE fields of a PTE, indicating to the PE's local cache that the corresponding coherence granule should transition to the MW state, and indicating to remote local caches that copies of the coherence granule should update their coherence state.