Page Table Entry Translation Counters for Memory Utilization
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Solution Overview
Problem
Conventional memory management systems face inefficiencies in measuring memory utilization due to the lack of detailed information on page frequency, as they rely on a single 'accessed' bit in page table entries, making it costly and inefficient to track page usage.
Innovation Solution
Incorporating n-bit translation counters within page table entry data structures to count the number of translations performed, allowing for more accurate measurement of memory utilization and informing TLB and page replacement policies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single 'accessed' bit is used in PTE to track page usage, then the memory management system can maintain simple PTE structure, but it cannot provide detailed information on page frequency and requires costly scanning to measure memory utilization
Solution Approach 1:
The patent segments the measurement function by dividing the tracking mechanism into multiple independent counter fields within the PTE structure. Each counter (e.g., access counter, modification counter, translation counter) independently tracks specific aspects of page usage, allowing precise measurement of different utilization metrics without requiring complex external scanning mechanisms.
Solution Approach 2:
The patent transitions from a single-bit tracking approach to a multi-dimensional counting system by introducing multiple counter fields with different bit widths (e.g., 8-bit access counter, 8-bit modification counter, 10-bit translation counter). This dimensional expansion enables simultaneous tracking of multiple utilization aspects, providing comprehensive measurement precision while maintaining efficient hardware implementation.
2Loss of information
If the operating system continually scans and clears 'accessed' control bits to measure memory utilization, then it can obtain utilization data, but the process becomes very inefficient and time-consuming
Solution Approach 1:
The patent implements preliminary action by pre-configuring multiple counter fields within the PTE structure that automatically accumulate usage statistics during normal page access operations. The access counter, modification counter, and translation counter are incrementally updated by hardware during page operations, so that when measurement is needed, the data is already prepared and available without requiring time-consuming scanning or clearing operations.
Solution Approach 2:
The patent enables self-service by designing the PTE structure with self-updating counter fields that automatically track page usage statistics through hardware increment operations during normal memory access. The counters serve themselves by continuously recording access, modification, and translation events without external intervention, eliminating the need for operating system scanning and clearing operations to gather utilization data.
3Measurement precision
If n-bit translation counters are included within PTE data structures to count translation times, then accurate memory utilization measurement is enabled, but the PTE structure and memory bandwidth requirements increase
Solution Approach 1:
The patent applies local quality by assigning different counter bit widths to different PTE fields based on their specific measurement needs. The access counter uses 8 bits for general access frequency, the modification counter uses 8 bits for write operations, and the translation counter uses 10 bits for TLB translation tracking. This localized optimization provides precise measurement for each metric while minimizing the total memory bandwidth consumption compared to using uniformly large counters throughout the PTE structure.
Data Source
AI summary
Memory management systems and methods are provided in which n-bit translation counters are included within page table entry (PTE) data structures to count of number of times that translations are performed using the PTEs of pages. For example, a method for managing memory includes: receiving a virtual address from an executing process, wherein the virtual address references a virtual page frame number (VPFN) in a virtual address space associated with the executing process; accessing a PTE for translating the VPFN to a page frame number (PFN) in physical memory; incrementing a n-bit translation counter within the accessed PTE in response to the translating; and accessing a memory location within the PFN in the physical memory, which corresponds to the virtual address.