PTI Semiconductor Package with Pillar-Top Interconnection
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Solution Overview
Problem
Conventional Package-On-Package (POP) stacked assemblies face limitations in reducing the stacking gap and package footprint due to the constraints of solder ball diameters and pitches, making it difficult to achieve thinner and smaller semiconductor packages with efficient vertical interconnections.
Innovation Solution
The Pillar-Top-Interconnection (PTI) configuration using the Molded-Interconnect-Substrate (MIS) process eliminates conventional molding thickness and stacking gaps by embedding a redistribution layer and metal pillars within a molding core, allowing for ultra-thin and compact semiconductor packages with zero gaps between stacked assemblies through repeated MIS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional solder ball interconnection is used in POP stacked assembly, then electrical connection between stacked packages is achieved, but the stacking gap and package footprint cannot be reduced further due to limitations of solder ball diameters and pitches
Solution Approach 1:
The patent extracts the interconnection function from the encapsulant material and relocates it to the substrate plane. Through-holes are formed in the substrate and filled with conductive material to create interconnection elements that extend through the substrate thickness, separating the interconnection function from the encapsulant and enabling thinner packages.
Solution Approach 2:
The patent transitions from surface-mounted solder ball interconnections to through-substrate vertical interconnections. By creating conductive paths through the substrate thickness dimension, the interconnection elements can be positioned at smaller pitches and eliminate the need for large stacking gaps required by spherical solder ball geometries.
2Adaptability or versatility
If through mold holes are drilled to expose peripheral pads for interconnections, then POP stacking is enabled, but the filled solder pastes cannot be shaped as solder balls and fabrication becomes difficult
Solution Approach 1:
The patent changes the geometric parameters of the interconnection elements from spherical solder balls to cylindrical or rectangular conductive fills within through-holes. This parameter change allows the use of conductive pastes or plating processes that can be precisely controlled to form consistent interconnection elements without requiring spherical shaping.
Solution Approach 2:
The through-holes are formed and prepared with conductive material before the encapsulation process. This preliminary action ensures that the interconnection elements are already in place and properly positioned, eliminating the need for subsequent shaping operations and ensuring precise alignment for stacked assembly.
3Quantity of substance
If interposer solder balls are encapsulated in the encapsulant, then vertical electrical interconnection is achieved, but the number and layout are limited by the diameters and pitches of the encapsulated solder balls
Solution Approach 1:
By moving interconnection elements to the substrate plane and forming them as through-holes, the patent enables denser packing arrangements. The interconnection elements can be positioned at smaller center-to-center distances since they are constrained by substrate hole patterns rather than by the diameter of spherical solder balls, allowing more interconnections per unit area.
4Length of moving object
If conventional molding thickness is used on IC substrate, then chip encapsulation is achieved, but the package height increases and ultra-thin POP stacked assembly cannot be achieved
Solution Approach 1:
The patent extracts the interconnection function from the encapsulant material and relocates it to the substrate plane through through-holes. This extraction allows the encapsulant to be made much thinner since it no longer needs to contain or support large solder balls, while chip encapsulation protection is maintained through the remaining encapsulant thickness.
Data Source
AI summary
Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.