Passive Tunable Integrated Circuit with BST Capacitors and Redistribution Layer

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Solution Overview

Problem

Conventional passive tunable integrated circuits (PTICs) with barium strontium titanate (BST) capacitors face challenges in die size optimization and stress management due to the placement of electrical contacts and bumps, which can lead to increased wafer area usage and stress-related issues.

Innovation Solution

The implementation of a semiconductor die with BST tunable capacitors and a redistribution layer that electrically couples contact pads and bumps directly over the capacitative area, eliminating the need for a leadframe and reducing stress through a reticulation pattern in the overlayer, allowing for a more efficient layout and smaller package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If electrical contacts and bumps are placed outside the capacitative area in conventional PTICs, then stress management is improved, but die size and wafer area usage increase

Engineering Contradiction:

Improvestress managementVSAvoiddie size

Core Design Contradiction:

Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

The patent merges the functions of electrical contacts and bumps with the capacitative area by placing them directly over the capacitative area. The redistribution layer integrates multiple functions (electrical coupling, stress relief, and area optimization) into a single structure, eliminating the need for separate contact regions outside the capacitative area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent uses the vertical dimension by implementing a redistribution layer with multiple layers (conductive layers and insulative layers) stacked above the capacitative area. This allows electrical contacts and bumps to be positioned over the capacitative area in the planar view while maintaining proper electrical isolation and connection through the vertical stacking of layers.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Strength

If a leadframe is used for packaging, then structural support is improved, but package size and production cost increase

Engineering Contradiction:

Improvestructural supportVSAvoidproduction cost

Core Design Contradiction:

StrengthVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the leadframe component from the packaging structure. The redistribution layer and die structure are designed to provide structural support independently without requiring a leadframe, thereby reducing package size and production cost while maintaining necessary structural integrity.

Inventive Principle:

Principle #2Taking out (Extraction)

3Device complexity

If contact pads are placed outside the capacitative area, then electrical coupling is simplified, but wafer space usage increases

Engineering Contradiction:

Improveelectrical couplingVSAvoidwafer space

Core Design Contradiction:

Device complexityVSArea of stationary object

Solution Approach 1:

The patent combines the capacitative area and contact pad locations into the same spatial region. The redistribution layer provides electrical coupling between BST capacitors and external connections while the contact pads are positioned over the capacitative area, eliminating the need for separate external contact regions and optimizing wafer space utilization.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables a smaller die size, more efficient layout, reduced wafer space usage, and lower production costs by placing all bumps and contact pads over the capacitative area, while also providing stress relief through the reticulation pattern, enhancing the overall performance and stability of the PTICs.

Implementation Method 1

Variable capacitors utilizing a BST layer vary capacitance through the application of a voltage

Methodology Applied

Scientific EffectCapacitance variation through voltage application: Dielectric Permittivity

Implementation Method 2

a plurality of holes arranged in a reticulation pattern adapted to reduce stress of the overlayer through the reticulation pattern

Methodology Applied

Scientific EffectStress relief through reticulation pattern: Stress Relaxation

Data Source

PatentUS9847287B2Passive tunable integrated circuit (PTIC) and related methods

Publication Date: 2017.12.19 SEMICON COMPONENTS IND LLC

AI summary

A passive tunable integrated circuit (PTIC) includes a semiconductor die (die) having a plurality of barium strontium titanate (BST) tunable capacitors. The plurality of BST tunable capacitors collectively define a capacitative area of the die. At least one electrical contact is electrically coupled with the plurality of BST tunable capacitors. A redistribution layer electrically couples the at least one electrical contact with at least one electrically conductive contact pad (contact pad). The at least one contact pad is located over the capacitative area. A bump electrically couples with the at least one contact pad and is located over the capacitative area. An electrically insulative layer couples between each contact pad of the PTIC and the plurality of BST tunable capacitors.