PTP Clock Redundancy in Ring Topology for Timing Loop Prevention

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Solution Overview

Problem

Precision timing protocols like PTP face challenges in maintaining synchronization accuracy due to packet delay variation and asymmetry in IP/MPLS networks, which can lead to synchronization errors and timing loops in ring topologies.

Innovation Solution

Implementing a ring topology with PTP nodes that include boundary clocks (BCs) and transparent clocks (TCs) to mitigate packet delay variation and asymmetry, using an alternate best master control algorithm (BMCA) for dynamic master selection and clock redundancy, and employing techniques to detect and break timing loops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PTP is implemented over IP/MPLS networks in ring topology, then timing synchronization can be provided across the network, but packet delay variation and asymmetry cause synchronization errors and timing loops

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidtiming accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

Boundary clocks (BCs) and transparent clocks (TCs) are introduced as intermediary devices between the PTP master and slave clocks in the ring topology. These intermediaries compensate for packet delay variation and asymmetry introduced by IP/MPLS network elements, thereby maintaining synchronization accuracy while enabling reliable timing distribution across the network.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system preemptively establishes clock redundancy with alternate master clocks before failures occur. When a timing loop or synchronization error is detected, the system can quickly switch to an alternate master clock, cushioning against the harmful effects of packet delay variation and asymmetry before they cause complete synchronization failure.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If clock redundancy is implemented with alternate master clocks, then reliability is improved, but device complexity increases due to dynamic master selection algorithms

Engineering Contradiction:
Improveclock redundancyVSAvoidmaster selection complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements dynamic master selection where boundary clocks can transition between slave and master roles based on real-time network conditions. The alternate best master control algorithm (ABMCA) enables clocks to dynamically switch roles and select alternate masters when timing loops are detected, providing reliability while managing complexity through standardized dynamic behavior.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors for timing loops and synchronization errors, providing feedback to the master selection algorithm. When a timing loop is detected, the feedback triggers a switch to an alternate master clock. This feedback mechanism manages the complexity of clock redundancy by automatically adjusting master selection based on actual network conditions rather than requiring complex preemptive configurations.

Inventive Principle:
Principle #23Feedback

3Stability of the object's composition

If timing loop detection and breaking techniques are employed, then synchronization stability is improved, but the system requires additional detection mechanisms increasing device complexity

Engineering Contradiction:
Improvesynchronization stabilityVSAvoiddetection mechanism complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The system employs feedback-based timing loop detection where boundary clocks monitor the synchronization messages circulating in the ring topology. When a timing loop is detected through message analysis and timestamp comparison, the system automatically triggers loop-breaking actions such as disabling affected ports or switching to alternate masters. This feedback approach provides synchronization stability while managing detection complexity through standardized monitoring procedures.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The PTP protocol itself provides built-in mechanisms for timing loop detection through its message exchange and timestamping features. Boundary clocks use the synchronization messages already circulating in the network to detect loops, rather than requiring separate dedicated detection mechanisms. This self-service approach improves synchronization stability while minimizing additional device complexity by utilizing existing protocol infrastructure.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9819541B2PTP over IP in a network topology with clock redundancy for better PTP accuracy and stability
Publication Date: 2017.11.14 CISCO TECHNOLOGY INC
  • US9819541B2 patent drawing
  • US9819541B2 patent drawing
  • US9819541B2 patent drawing

AI summary

In one embodiment, a technique for implementing precision time protocol (PTP) over a packet transport (e.g., IPv4, IPv6, etc.) with clock redundancy is provided. The technique may involve maintaining clock synchronization by a PTP node, where the PTP node participates in an exchange of one or more messages with a current master node and at least one connected node that is a slave to the PTP node. The technique may also involve detecting one or more conditions that prompt a switch to a new master PTP node. The technique may further involve selecting the new master PTP node, and determining, based on the selection, whether the new master PTP node is a slave to the PTP node. The technique may yet further involve taking action, based on the determination, to indicate to the new master PTP node that the PTP node is not a suitable master.