PTP Boundary Clock Source Selection Across IWF Profile Translation

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Solution Overview

Problem

The complexity of implementing mixed PTP architectures using IWFs that translate between different profiles complicates the selection of the best master clock, leading to suboptimal clock source choices due to hidden upstream clock conditions.

Innovation Solution

Utilizing reserved bits in the PTP announce packet flags to indicate IWF profile translations, allowing boundary clock nodes to make informed decisions based on priority levels and clock conditions, thereby enhancing the Best Master Clock Algorithm (BMCA) in networks with Assisted-PTS and FTS architectures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If IWF profile translation is implemented to connect different PTP network segments, then network compatibility and adaptability are improved, but the complexity of clock source selection increases and measurement precision of upstream clock conditions deteriorates

Engineering Contradiction:
Improvenetwork compatibilityVSAvoidclock source selection complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism (the IWF priority indication in announce packets) that mediates between different PTP profile segments. This intermediary provides the necessary information about upstream clock conditions through the IWF translation process, enabling boundary clock nodes to make informed decisions without increasing selection complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary action by pre-indicating the IWF priority level in the announce packets before the clock selection process. This allows boundary clock nodes to have advance information about upstream clock conditions, eliminating the need for complex real-time analysis during clock source selection

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If standard PTP announce packets are used without IWF priority indication, then packet structure simplicity is maintained, but loss of information about upstream clock conditions occurs leading to suboptimal clock selection

Engineering Contradiction:
Improvepacket structure complexityVSAvoidupstream clock conditions information
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The patent changes the parameters of the existing PTP announce packet by utilizing reserved bits in the flags field to encode IWF priority information. This approach maintains the overall packet structure while adding critical information about upstream clock conditions, preventing information loss without increasing structural complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent makes the announce packet multi-functional by having it serve both its original purpose of clock advertisement and the additional function of conveying IWF priority information. This universal approach allows a single packet structure to provide comprehensive clock selection information without requiring separate communication mechanisms

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4595288B1System and method for selecting PTP sources in a network with IWF assisted boundary clocks
Publication Date: 2026.02.18 CIENA CORP
  • EP4595288B1 patent drawingFigure 1A
  • EP4595288B1 patent drawingFigure 1B
  • EP4595288B1 patent drawingFigure 2

AI summary

Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: receiving an indication of a priority level of an interworking function used by a boundary clock node; and selecting a best master clock using an algorithm that considers the priority level of the boundary clock node. Other embodiments are disclosed.