PtSe2 Source-Drain Structure for Low-Tunneling Fin Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with subthreshold slope and contact resistance in transistor devices.
Innovation Solution
The use of semimetallic source/drain structures formed from 2D material layers like PtSe2, where the conduction and valence bands are at different symmetry k-points, reduces unwanted tunneling effects and improves subthreshold slope performance by suppressing source-to-drain tunneling, and lowers contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process difficulty increases and device reliability deteriorates
Solution Approach 1:
The patent changes the material parameter from conventional semiconductor to 2D material with semimetallic properties, which fundamentally alters the electrical characteristics and enables reliable device operation at smaller feature sizes by suppressing tunneling effects
Solution Approach 2:
The patent employs composite material structures combining 2D material layers with specific thickness ranges (greater than 2 nm for semimetallic properties, less than 2 nm for semiconductor properties) to achieve both high reliability and scalability
2Ease of manufacture
If conventional source/drain structures are used in scaled devices, then manufacturing is simpler, but subthreshold slope performance deteriorates due to unwanted tunneling effects
Solution Approach 1:
The patent changes the material composition and thickness parameters of source/drain structures to 2D materials with semimetallic properties (thickness greater than 2 nm), which fundamentally suppresses tunneling effects and improves subthreshold slope without complicating the manufacturing process
3Reliability
If 2D material layers with semimetallic properties are used, then tunneling effects are suppressed and subthreshold slope improves, but contact resistance may increase
Solution Approach 1:
The patent applies different 2D material layer thicknesses in different device regions: thicker layers (greater than 2 nm) in source/drain regions for semimetallic properties and lower tunneling, and thinner layers (less than 2 nm) in channel regions for optimal conductance, thereby optimizing both subthreshold slope and contact resistance locally
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the subthreshold slope and reduces resistance in semiconductor devices, improving their performance and efficiency by utilizing semimetallic properties to minimize tunneling and optimize channel conductance.
Implementation Method 1
the conduction and valence bands are at different symmetry k-points, reduces unwanted tunneling effects and improves subthreshold slope performance by suppressing source-to-drain tunneling
Data Source
AI summary
A method includes forming a semiconductor fin protruding above a substrate; forming a first 2D material layer across the semiconductor fin; depositing a gate material layer over the first 2D material layer; etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure; laterally growing a second 2D material layer from the patterned first 2D material layer to beyond the gate structure; after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe2.