P-Type Gate Driver Circuit for Fast, Stable Display Scanning
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Solution Overview
Problem
Existing display technologies face challenges in improving response speed, minimizing bezel size, and enhancing driving reliability and stability of gate drivers in display apparatuses.
Innovation Solution
Incorporation of a gate driver with P-type transistors, including a node controller, dummy signal output unit, and scan signal output unit, which minimizes rising and falling times of scan signals and reduces bezel size while improving driving reliability by suppressing positive bias temperature stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a gate driver uses conventional transistor configurations, then the device can operate, but the response speed is insufficient
Solution Approach 1:
The patent changes the transistor type parameter from conventional N-type to P-type transistors in the gate driver circuit. This parameter change enables the circuit to achieve both fast response speed and high driving reliability by utilizing the unique characteristics of P-type transistors, which can operate at higher speeds while maintaining stability through their inherent device characteristics.
2Area of stationary object
If the gate driver circuit area is reduced, then the bezel size is minimized, but the driving reliability may be compromised
Solution Approach 1:
The patent merges multiple functional units (node controller, dummy signal output unit, and scan signal output unit) into a single integrated gate driver circuit. This consolidation reduces the overall circuit area, thereby minimizing the bezel size, while the P-type transistor configuration ensures that driving reliability is maintained despite the reduced area.
3Speed
If the scan signal rising and falling times are reduced, then the response speed improves, but the driving reliability may be affected
Solution Approach 1:
The patent utilizes the specific electrical characteristics of P-type transistors to achieve rapid scan signal transitions (reducing rising and falling times) while maintaining driving reliability. The P-type transistors' inherent properties allow for fast switching without compromising the stability and reliability of the gate driver operation.
Data Source
AI summary
A gate driver may include a plurality of stages, each of the plurality of stages includes: a node controller configured to control voltages of a Q node, a Q2 node, a Qb node, and a QN node connected to transistors based on a first clock signal and a second clock signal; a dummy signal output unit configured to output a dummy signal based on the voltages of the Q node and the Qb node; and a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QN node, and a transistor configured to output a gate low voltage according to a voltage of the Q node as the scan signal, among a configuration of the scan signal output unit, may be a P-type transistor.