P-Type TFT Buffer Circuit for Low-Power Display Driving
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of display panels and driving circuits in active matrix liquid crystal displays and organic electro-luminescence displays requires multiple masks and additional processes for N-type and P-type transistors, leading to decreased process yield, increased costs, and operational reliability issues, particularly due to thermal damage of N-type thin film transistors during element driving.
Innovation Solution
A buffer circuit design utilizing P-type thin film transistors with a specific configuration of transistors and capacitors that allows stable low-power operation and reduces the impact of process variations, including a first transistor for transmitting a power source voltage, a second transistor for inverted voltage transmission, and a capacitor to maintain voltage ranges for transistor switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If N-type and P-type transistors are integrated using CMOS thin film transistors, then the display panel and driving circuit can be integrated, but process yield decreases and process cost increases due to multiple masks and additional processes
Solution Approach 1:
The patent uses only P-type thin film transistors for both the display panel driving circuits and the buffer circuit, eliminating the need for separate N-type and P-type transistor fabrication processes. This homogeneous approach using a single transistor type resolves the technical contradiction by maintaining integration capability while avoiding the process complexity and yield loss associated with CMOS fabrication requiring multiple masks and additional voltage control processes
2Ease of operation
If N-type thin film transistors are used in the buffer circuit, then the buffer can drive low level output signals, but the transistors suffer thermal damage during element driving causing characteristic degradation
Solution Approach 1:
Instead of using N-type transistors to drive low level output signals, the patent inverts the approach by using P-type thin film transistors with a circuit configuration where the buffer output can achieve low voltage levels. The inversion lies in using the complementary transistor type (P-type instead of N-type) while achieving the same functional goal through different circuit topology and operating principles
3Reliability
If P-type thin film transistors are used in the buffer circuit, then thermal damage is avoided, but the buffer cannot efficiently drive low level output signals
Solution Approach 1:
The patent changes the operating parameters and circuit configuration of P-type thin film transistors to enable low voltage output capability. By adjusting the circuit topology and operating conditions rather than changing the transistor type, the buffer achieves both high reliability (avoiding thermal damage) and the ability to drive low level output signals
4Use of energy by moving object
If additional processes are used to control threshold voltage of N-type and P-type transistors, then the buffer can be driven with low power, but process cost increases and reproducibility problems occur
Solution Approach 1:
The patent achieves low power operation with P-type thin film transistors without requiring additional threshold voltage control processes. The homogeneous use of a single transistor type eliminates the need for separate process steps to control different threshold voltages, thereby reducing process cost and improving reproducibility while maintaining efficient low-power operation
Data Source
AI summary
A buffer and a driving method thereof are provided. The buffer includes a first transistor for transmitting a first power source voltage to an output terminal according to an input voltage, a second transistor for transmitting an inverted voltage of the input voltage to the output terminal, a capacitor including a first terminal coupled to a gate of the second transistor and a second terminal configured to be input with a first level voltage or a second level voltage according to the input voltage, and a third transistor for transmitting a second power source voltage to the gate of the second transistor according to the input voltage.