Public Buffer Card Co-Processing Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computer systems, the processing capability of a single computer is limited, leading to bottlenecks in large-scale computing scenarios, and existing co-processing architectures result in high memory overheads and low co-processing speeds due to memory bandwidth limitations and data transfer delays.
Innovation Solution
A computer system with a public buffer card that acts as a data buffer channel between compute nodes and co-processor cards, allowing to-be-processed data to be stored and allocated to idle co-processor cards for processing without involving the compute node's memory, thereby reducing memory overheads and increasing co-processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred through the memory of the compute node for co-processing, then the data transmission channel is established, but the memory overheads increase and the co-processing speed decreases
Solution Approach 1:
The patent introduces a public buffer card as an intermediary component between compute nodes and co-processor cards. This public buffer card serves as a shared data transmission channel that eliminates the need for compute node memory to handle co-processing data transfers. The management board allocates data to the public buffer card, which then directly interfaces with co-processor cards, thereby reducing memory overheads and increasing co-processing speed.
2Speed
If the memory of the compute node is used as a data transmission channel, then data can be transferred between compute node and co-processor card, but the memory bandwidth and delay limits the co-processing speed
Solution Approach 1:
The patent segments the data transmission function from the compute node memory by introducing a dedicated public buffer card. This separates the co-processing data transmission path from the general-purpose memory system, allowing the public buffer card to be optimized specifically for high-speed co-processing data transfers without being constrained by general memory bandwidth limitations.
3Adaptability or versatility
If a PCIE co-processor card architecture is used, then coprocessors can aid compute nodes in task processing, but the data must be transferred through compute node memory which reduces efficiency
Solution Approach 1:
The public buffer card serves as a universal data transmission channel that can serve multiple compute nodes and multiple co-processor cards simultaneously. This multi-functional design allows any compute node to access any co-processor card through the shared public buffer card, providing versatile co-processing capability while maintaining high efficiency through direct data transfer paths.
Data Source
AI summary
An embodiment of the present invention discloses a co-processing acceleration method, including: receiving a co-processing request message which is sent by a compute node in a computer system and carries address information of to-be-processed data; according to the co-processing request message, obtaining the to-be-processed data, and storing the to-be-processed data in a public buffer card; and allocating the to-be-processed data stored in the public buffer card to an idle co-processor card in the computer system for processing. An added public buffer card is used as a public data buffer channel between a hard disk and each co-processor card of a computer system, and to-be-processed data does not need to be transferred by a memory of the compute node, which avoids overheads of the data in transmission through the memory of the compute node, and thereby breaks through a bottleneck of memory delay and bandwidth, and increases a co-processing speed.