PUF Chip Capacitor Connection via Deposition Layer Openings
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Solution Overview
Problem
Current fabrication methods for physical unclonable function (PUF) chips result in low security due to the potential for identical capacitor connection states among chips on the same wafer, compromising digital and financial security.
Innovation Solution
A method involving the formation of an array of spaced electrode plates on a top metal connection layer, a deposition layer between these plates forming capacitors, and a conductive coating layer with randomly distributed conductive particles to create unique and unpredictable capacitor connections, preventing identical chip states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form capacitors on a wafer, then manufacturing efficiency is maintained, but security is compromised due to identical capacitor connection states among chips on the same wafer
Solution Approach 1:
The patent applies preliminary action by forming openings in the deposition layer before forming the upper electrode plates. This preliminary structuring of the deposition layer with pre-positioned openings ensures that when conductive material is deposited to form upper electrodes, the connections between capacitors are predetermined and unique to each chip's physical variations, preventing identical connection states across chips on the same wafer.
Solution Approach 2:
The patent implements local quality by creating position-dependent variations in capacitor connections through the pre-formed openings in the deposition layer. Each local region (chip location) on the wafer develops unique capacitor connection patterns based on the specific geometry and positioning of openings relative to electrode plates, ensuring that chips at different locations have distinct electrical characteristics even though they are fabricated using the same overall process.
2Productivity
If identical capacitor connection states are allowed among chips, then manufacturing consistency is maintained, but digital and financial security are compromised
Solution Approach 1:
The patent applies parameter changes by utilizing variations in the physical parameters of the deposition layer openings (position, size, shape) to create different capacitor connection states. By controlling the geometry and location of openings in the deposition layer, the patent ensures that electrical parameters (connection patterns) vary between chips while maintaining manufacturing process consistency, thus achieving both productivity and security requirements.
Data Source
AI summary
A physical unclonable function (PUF) chip is provided. The physical unclonable function (PUF) chip includes a chip with a top metal connection layer, an array of spaced electrode plates on the top metal connection layer of the chip, a deposition layer, on the top metal connection layer between each two adjacent electrode plates. An opening is formed between the each two adjacent electrode plates in a row, and each two adjacent electrode plates are tangential to the opening formed between the two adjacent electrode plates. The physical unclonable function (PUF) chip further includes a conductive coating layer on the chip and the conductive coating layer includes conductive particles with randomly distributed size, and a package substrate, packaged with the chip including the conductive coating layer.