PUF Cell Defect Engineering via STI and Gate Epitaxy
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Solution Overview
Problem
Existing methods for fabricating physically unclonable function (PUF) devices do not effectively utilize unique variations in integrated circuits to create secure, unclonable features.
Innovation Solution
A method for fabricating a PUF device involves defining a PUF cell region on a substrate and forming a defect by creating a shallow trench isolation (STI), patterning gate material layers, and forming an epitaxial layer between the gate structures to establish a connection, thereby creating a unique defect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to manufacture integrated circuits, then manufacturing precision and consistency are improved, but the ability to create unique variations for security purposes deteriorates
Solution Approach 1:
The patent applies preliminary action by intentionally creating defects during the fabrication process before the device is completed. Specifically, the method introduces defects into PUF cell regions during manufacturing through controlled processes such as forming shallow trench isolation or creating incomplete transistor structures. This preliminary introduction of variations allows the device to have unique characteristics while still being manufactured using conventional precise processes, thus resolving the contradiction between manufacturing consistency and unique variation capability.
2Reliability
If defects are introduced to create unique features, then security and unclonability are improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the defect creation process with existing fabrication steps. Instead of adding separate defect introduction steps, the method incorporates defect creation into standard processes such as shallow trench isolation formation, gate material deposition, or epitaxial layer growth. By combining multiple functions into single process steps, the patent introduces unique variations for security purposes without significantly increasing manufacturing complexity, thus resolving the contradiction between security enhancement and process simplicity.
3Reliability
If unique variations are created in PUF devices, then predictability of output decreases and security increases, but control over device characteristics deteriorates
Solution Approach 1:
The patent applies local quality by creating variations only in specific PUF cell regions while maintaining standard fabrication quality in other parts of the device. The method selectively introduces defects or variations into designated PUF cells through localized processing steps, such as selective shallow trench isolation or targeted epitaxial growth. This approach ensures that unique variations are created where needed for security purposes while maintaining precise control over the overall device manufacturing, thus resolving the contradiction between security through unpredictability and manufacturing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a PUF device with a unique, unclonable feature that enhances security by making it difficult to predict the output, thus increasing the level of security.
Implementation Method 1
forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer
Data Source
AI summary
A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.


