PUF Memory Cell Layout Using Multiple Elements Against Cloning
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Solution Overview
Problem
Existing physical unclonable functions (PUFs) in semiconductor devices lack sufficient security due to reliance on single memory elements for bit storage, making them vulnerable to unauthorized duplication and tampering.
Innovation Solution
Implementing memory devices with multiple memory elements per cell, where each element has a unique state, ensuring only one is programmed during operations, and reading currents through these elements to determine the logic values, enhancing security by obscuring the specific element storing the bit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory elements are used per cell, then security is improved, but device complexity increases
Solution Approach 1:
The memory cell is segmented into multiple memory elements (first memory element and second memory element), each capable of storing a bit. This segmentation allows the system to improve security by making it difficult to determine which specific element stores the actual data bit, while the complexity is managed through systematic control circuitry that handles the multiple elements.
2Object-affected harmful factors
If multiple memory elements are used per cell, then resistance to unauthorized duplication is improved, but manufacturing complexity increases
Solution Approach 1:
The memory cell is segmented into multiple memory elements (first memory element and second memory element), each capable of storing a bit. This segmentation allows the system to improve security by making it difficult to determine which specific element stores the actual data bit, while the complexity is managed through systematic control circuitry that handles the multiple elements.
Data Source
AI summary
A method includes: programming a first bit of a physical unclonable function into a first memory cell; and generating, by a first memory circuit in the first memory cell, a first current indicating a logic value of the first bit. The programming the first bit includes: turning on a first switch in the first memory circuit and at least one second switch in at least one second memory circuit in the first memory cell in response to a first bit line signal, to program one of the first memory circuit and the at least one second memory circuit while rest of the first memory circuit and the at least one second memory circuit is not programmed, according to the first bit line signal. A memory device and a system are also disclosed herein.


