PUF Memory Cell with Parallel Access Transistors for Stable Bitstring Generation
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Solution Overview
Problem
Current on-chip Physically Unclonable Function (PUF) architectures face challenges in consistently generating the same random number due to variations in operating conditions such as temperature and voltage, requiring less secure postprocessing algorithms to compensate.
Innovation Solution
The proposed solution involves an on-chip circuit with a memory cell structure that includes multiple variable resistors and transistors, where the gates of access transistors are connected to specific wordlines to apply controlled write and read bias conditions, allowing for one-time programming and stable resistance state switching, ensuring consistent bitstring generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current on-chip PUF architectures are used, then random number generation is implemented, but variations in operating conditions (temperature, voltage) cause difficulty in repeatedly generating the exact same random number
Solution Approach 1:
The patent applies preliminary action by performing one-time programming of the memory cell during manufacturing to establish a stable resistance ratio between the first and second variable resistors. This pre-established configuration ensures that the PUF consistently generates the same random number across varying operating conditions, eliminating the need for postprocessing algorithms and achieving reliable repeated generation without being affected by temperature or voltage variations.
2Reliability
If postprocessing algorithms are applied to compensate for operating condition variations, then random number consistency is improved, but security is reduced
Solution Approach 1:
The patent eliminates the need for postprocessing algorithms by performing preliminary configuration during manufacturing. The memory cell is programmed once to establish a stable resistance ratio that inherently resists operating condition variations. This approach maintains full security by avoiding any information loss associated with postprocessing, while achieving consistent random number generation across temperature and voltage variations.
3Reliability
If multiple variable resistors and parallel-connected transistors are used in memory cells, then consistent bitstring generation is achieved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory cell into distinct functional components: a first variable resistor with a first access transistor for generating a first resistance value, and a second variable resistor with a second access transistor for generating a second resistance value. This segmentation allows independent control and measurement of each resistance value, enabling consistent bitstring generation through ratio comparison while organizing the complexity into manageable, modular units that can be systematically integrated into the PUF array.
Solution Approach 2:
The patent applies universality by designing the memory cell structure to serve multiple functions: the first and second variable resistors simultaneously serve as both the storage element and the sensing element, the access transistors serve as both switches and measurement devices, and the same memory cell infrastructure is used for both one-time programming and repeated readout operations. This multi-functionality reduces overall device complexity by eliminating redundant components while maintaining reliable bitstring generation.
Data Source
AI summary
Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.