PUF MOS Transistor Structure for Native Cryptographic Key Generation
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Solution Overview
Problem
Traditional IoT encryption technologies face risks of user identity theft, cryptographic key loss, and high operational costs due to frequent access to stored passwords, which are not adequately addressed by existing methods.
Innovation Solution
A physically unclonable function device is fabricated using a combination of enhancement-mode and depletion-mode MOS transistors with controlled ion implantation to create random conduction states, generating a native cryptographic key for immediate verification and decryption without additional software support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional encryption technology stores cryptographic keys in hardware apparatus, then decryption functionality is achieved, but security risks increase due to potential key loss and identity theft
Solution Approach 1:
The patent extracts the cryptographic key from traditional storage media and embeds it directly into the transistor device structure itself. The key is physically encoded in the doping patterns and transistor characteristics, making it inseparable from the hardware and impossible to lose or steal independently.
Solution Approach 2:
The transistor device automatically generates and maintains its cryptographic key through its inherent physical properties and manufacturing variations. The device serves itself by using its own structural characteristics (doping concentrations, channel dimensions) as the cryptographic key, eliminating the need for external key management.
2Ease of operation
If cryptographic keys are stored in memory of hardware apparatus, then decryption is enabled, but operating cost increases due to frequent access requirements
Solution Approach 1:
The patent merges the cryptographic key storage function with the transistor's structural properties. The key is embedded in the physical characteristics of the transistor (doping patterns, channel dimensions) rather than being stored separately in memory, combining the key management and processing functions into a single integrated structure.
Solution Approach 2:
The cryptographic key is pre-encoded into the transistor device structure during manufacturing through specific doping patterns and dimensional configurations. This preliminary encoding eliminates the need for frequent key access during operation, as the key is inherently present in the device's physical state.
3Ease of operation
If cryptographic keys are stored in hardware apparatus, then decryption functionality is achieved, but access time increases due to frequent memory access
Solution Approach 1:
The patent merges the cryptographic key storage function with the transistor's structural properties. The key is embedded in the physical characteristics of the transistor (doping patterns, channel dimensions) rather than being stored separately in memory, combining the key management and processing functions into a single integrated structure.
Solution Approach 2:
The cryptographic key is pre-encoded into the transistor device structure during manufacturing through specific doping patterns and dimensional configurations. This preliminary encoding eliminates the need for frequent key access during operation, as the key is inherently present in the device's physical state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances security by preventing cryptographic key loss and identity theft, reducing power consumption and access time, while providing a native cryptographic key for rapid decryption.
Implementation Method 1
a plurality of ion implantation processes are performed to form a plurality of doped well regions and doped channel regions
Data Source
AI summary
A PUF device includes a first transistor that has a first well with a first conductivity and a first channel region with a second conductivity, a second transistor that has a second well and a second channel region both with the first conductivity, and a reading circuit. When a gate-source voltage applied to these transistors is equal to 0, the first transistor and the second transistor are both in an off state. The reading circuit is electrically connected to the first transistor and the second transistor, and is used to read a plurality of first conduction states of the first transistors and the second transistor, and then to output a first set of numerical values.