PUF Reset Circuit for Voltage Tampering Protection
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Solution Overview
Problem
Existing methods for preventing cell retention failure attacks in physically unclonable function (PUF) generators, such as SRAM-based PUFs, are either costly, increase boot time, or require complex cryptographic primitives that exceed the capabilities of resource-constrained devices.
Innovation Solution
A novel circuit design for a PUF generator that includes a PUF cell array, a PUF control circuit, and a reset circuit, which detects supply voltage tempering events and resets bit cells to their initial logical states, preventing cell retention failure attacks by locking bit lines and word lines to specific logical states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate SRAM block is used for building the PUF, then security against cell retention failure attacks is improved, but implementation cost and device complexity increase significantly
Solution Approach 1:
The patent merges the PUF generation function with the existing SRAM memory block by utilizing the same storage cells for both data storage and PUF generation. The memory cells are configured to generate PUF bits through controlled voltage lowering that causes retention failures, eliminating the need for a separate dedicated SRAM block for PUF construction while maintaining security against cell retention failure attacks.
2Reliability
If the device waits for stored memory values to decay before reading data after power tempering detection, then security is improved, but boot time increases significantly
Solution Approach 1:
The patent implements preliminary action by detecting power tempering events and immediately resetting the affected memory cells to their initial states before PUF bit generation. This proactive approach prevents the security vulnerability without requiring the device to wait for natural decay, thereby maintaining fast boot times while ensuring security.
3Reliability
If complex cryptographic primitives are used to obfuscate PUF response bits, then security is improved, but device complexity and resource requirements exceed capabilities of resource-constrained devices
Solution Approach 1:
The patent applies self-service by designing the memory cell configuration and voltage control mechanism to inherently generate secure PUF bits through controlled retention failures. The system uses its existing memory infrastructure and voltage regulation capabilities to achieve security without requiring external complex cryptographic primitives, making it suitable for resource-constrained devices.
Data Source
AI summary
Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.