Threshold Decoder for PUF Error Correction Using Simplex Syndromes
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Solution Overview
Problem
Existing PUF reconstruction methods face challenges in efficiently determining the true PUF value from varying bit sequences due to random errors, requiring complex hardware and error correction mechanisms.
Innovation Solution
The use of a decoder based on a simplex code, which implements a feedback shift register to calculate a syndrome and combine it with a reference syndrome, allowing for efficient error correction and threshold-decodable operations to recover the true PUF value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used to compensate for bit sequence variations in PUF generation, then the reliability of PUF output is improved, but the hardware complexity and computation complexity increase
Solution Approach 1:
The patent transforms the PUF bit sequence into a different parameter domain by calculating a syndrome value using a feedback shift register that implements a specific code (e.g., simplex code or BCH code). This parameter transformation allows the system to work with syndrome values rather than raw bit sequences, enabling more efficient error correction with reduced hardware complexity.
Solution Approach 2:
The patent introduces a syndrome calculator as an intermediary component that mediates between the PUF bit sequence and the error correction process. The syndrome value acts as an intermediate representation that captures error information in a compact form, allowing the majority logic unit to perform error correction more efficiently without directly processing the full bit sequence.
2Reliability
If conventional error correction methods are used to compensate for bit sequence variations in PUF generation, then the reliability of PUF output is improved, but the computation complexity increases
Solution Approach 1:
The patent segments the error correction process into distinct functional stages: syndrome calculation using a feedback shift register, majority logic evaluation, and correction application. This segmentation allows each stage to be optimized independently, with the syndrome calculation handling the heavy computational burden through hardware-efficient shift register operations rather than complex software algorithms.
Solution Approach 2:
The patent employs feedback mechanisms where the syndrome calculator continuously processes bit sequences and the majority logic unit uses the syndrome values to determine corrections. The feedback shift register structure inherently provides efficient feedback loops that reduce computation complexity by reusing previous calculation states rather than performing redundant computations.
3Productivity
If the same physical object produces the same bit sequence each time, then the PUF generation efficiency is improved, but this is typically not achievable due to random errors
Solution Approach 1:
The patent performs preliminary syndrome calculation on incoming bit sequences before full error correction is needed. By pre-processing the bit sequences through the feedback shift register to generate syndrome values, the system prepares error correction data in advance, enabling faster recovery and improving overall PUF generation efficiency while maintaining reliability.
Data Source
AI summary
A decoder includes a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.