PUF Via Size Variation for Balanced Bit Yield
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Solution Overview
Problem
Existing PUF generation methods face challenges in maintaining optimal via sizes across different wafers and chips due to varying process variations, leading to imbalanced bit values and reduced yield, especially in security applications where true randomness is crucial.
Innovation Solution
An apparatus and method that generate digital values using physically unclonable functions (PUFs) with varying via sizes within an effective range, applying parameters such as via size to ensure equal probabilities of '0' and '1', and performing logical operations like XOR to select a first digital value meeting predesignated conditions, thereby increasing yield and randomness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed via size is used to generate PUFs, then the manufacturing process is simple, but the bit values become imbalanced and yield decreases due to process variations
Solution Approach 1:
The patent applies different via sizes to different PUFs within the same chip, creating local variation in the via dimensions. This local quality differentiation ensures that each PUF experiences unique process variations, preventing bit value imbalance while maintaining manufacturability through a standardized via formation process.
Solution Approach 2:
The patent systematically varies the via size parameter across different PUFs to optimize bit value distribution. By changing this physical parameter during manufacturing, the system achieves balanced bit values and improved yield without requiring complex post-processing or additional manufacturing steps.
2Reliability
If via size is optimized for one wafer, then bit value balance improves, but the optimal size changes due to process variations across different wafers and chips
Solution Approach 1:
The patent implements a dynamic approach where via sizes are not fixed but are determined based on the specific process conditions of each wafer and chip. This dynamic adaptation allows the system to maintain optimal bit value balance across different manufacturing batches by adjusting via sizes according to actual process variations.
Solution Approach 2:
The patent incorporates feedback mechanisms where the actual via sizes formed during manufacturing are measured and used to determine the optimal via size for each PUF. This feedback loop enables the system to adapt to process variations and maintain bit value balance across different wafers and chips.
3Reliability
If multiple passes of PUF generation are performed to determine optimal via size, then bit value balance improves, but manufacturing time and complexity increase
Solution Approach 1:
The patent performs preliminary actions by pre-determining via sizes within an effective range during the manufacturing process itself, rather than requiring separate optimization passes after chip fabrication. This preliminary action integrates the via size optimization into the standard manufacturing flow, eliminating additional time-consuming steps while achieving bit value balance.
Data Source
AI summary
Provided is an apparatus for generating digital values to provide a random digital value. The apparatus may generate the digital value based on a semiconductor process variation. The apparatus may include a generating unit to generate a plurality of digital values, based on the semiconductor process variation, and a processing unit to process the digital values and to provide a first digital value. The generating unit may include a plurality of physically unclonable functions (PUFs). A parameter may be differently applied to the PUFs, and the PUFs may generate the digital values.