PUF Cell Voltage Screening for Near-Zero Bit Error Rate
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Solution Overview
Problem
Current security technologies using physically unclonable function (PUF) circuits face challenges in maintaining a low bit error rate (BER), leading to increased complexity and power consumption due to the need for error checking and correction logic, and require extensive testing to identify unstable PUF cells.
Innovation Solution
A PUF circuit design that includes a plurality of PUF cells generating output voltages by dividing a power voltage, a reference voltage generator producing multiple reference voltages to determine data values and validity, and a comparison circuit to screen out unstable cells, setting a 'dead zone' to reduce bit error rates and simplify testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PUF circuits are used to generate security keys, then security functionality is provided, but bit error rate increases leading to higher complexity and power consumption for error correction
Solution Approach 1:
The patent applies preliminary action by performing extensive testing and identification of unstable PUF cells during the manufacturing process, before the PUF circuit is deployed for security operations. This allows unstable cells to be screened out and excluded from key generation, preventing bit errors from occurring in the first place rather than requiring complex error correction during operation.
Solution Approach 2:
The patent merges the testing and cell identification functions with the PUF circuit fabrication process itself. By integrating these functions, the system achieves reliable key generation with minimal additional complexity, as the testing infrastructure is combined with the production workflow rather than being a separate post-processing step.
2Reliability
If conventional PUF circuits operate without extensive testing, then device area and power consumption are reduced, but bit error rate increases requiring error correction logic
Solution Approach 1:
The patent performs cell stability testing and identification during manufacturing before deployment. This preliminary action ensures that only stable cells are used for key generation, eliminating the need for power-consuming error correction operations during runtime and achieving near-zero bit error rates without continuous energy expenditure on verification.
3Reliability
If conventional PUF circuits skip stability testing, then manufacturing time and cost are reduced, but unstable cells cause higher bit error rates
Solution Approach 1:
The patent merges the stability testing and cell identification processes with the PUF circuit manufacturing workflow. By integrating these functions, the system achieves reliable key generation with minimal additional manufacturing complexity, as the testing infrastructure is combined with the production process rather than being a separate post-processing step.
Solution Approach 2:
The patent performs extensive testing and identification of unstable PUF cells during the manufacturing process itself, before the PUF circuit is deployed for security operations. This preliminary action ensures that unstable cells are screened out and excluded from key generation, preventing bit errors from occurring in the first place.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces the bit error rate to near zero, minimizing the need for error correction logic, reducing the PUF system's area and power consumption, and simplifying the testing process by identifying and excluding unstable PUF cells.
Implementation Method 1
each configured to generate an output voltage by dividing a power voltage based on at least two resistors
Implementation Method 2
a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage by dividing the power voltage based on a resistor string
Implementation Method 3
a comparison circuit configured to compare the output voltages of the plurality of PUF cells with each of the first reference voltage, the second reference voltage and the third reference voltage
Data Source
AI summary
A physical unclonable function (PUF) circuit and a PUF system including the same are provided. The PUF circuit includes a plurality of PUF cells each configured to generate an output voltage by dividing a power voltage, a reference voltage generator configured to generate a first reference voltage by dividing the power voltage, and a comparing unit configured to sequentially compare the output voltages of the plurality of PUF cells with the first reference voltage to output data values of the plurality of PUF cells.