Pull-Back Substrate Layout for Thermal Crack Resistance
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Solution Overview
Problem
Power semiconductor module substrates with pull-back designs face increased risks of cracks in metallization layers when heated, due to high tensions in the dielectric insulation layer, which can lead to solder leaks and mechanical damage.
Innovation Solution
A substrate design featuring a dielectric insulation layer with alternating sections of full pull-back and reduced or no pull-back, where the difference in distances between the metallization layers and the dielectric insulation layer's edge varies, reducing tensions and crack formation risks by distributing stress more evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a pull-back design is used where the second metallization layer is smaller than the first metallization layer, then the solder area is reduced and the risk of solder leak and solder splash is reduced, but the risk of cracks forming in the metallization layers increases when heated
Solution Approach 1:
The outer edge of the dielectric insulation layer is divided into multiple sections (first sections and second sections) with different pull-back characteristics. The first sections have a first pull-back distance while the second sections have a second pull-back distance, segmenting the uniform structure into functional zones that balance solder protection and stress distribution.
Solution Approach 2:
Different sections of the outer edge are assigned different pull-back distances based on local requirements. Areas prone to solder leakage receive larger pull-back for protection, while other areas maintain smaller pull-back to reduce thermal stress and prevent cracking, creating localized optimal conditions throughout the substrate.
2Area of moving object
If the size of the second metallization layer is made smaller than the first metallization layer, then the mounting surface for semiconductor bodies is maximized, but the tension in the dielectric insulation layer increases when heated
Solution Approach 1:
The dielectric insulation layer's outer edge is segmented into sections with different pull-back distances, allowing the mounting surface area to be maximized in certain regions while distributing thermal tension across varied geometric zones, preventing concentration of stress in any single area.
Solution Approach 2:
The substrate structure implements local quality by providing different pull-back characteristics in different sections, enabling the first metallization layer to achieve maximum mounting surface area while the varied second section geometries locally manage thermal stress distribution to prevent excessive tension.
3Object-affected harmful factors
If the pull-back distance is increased to reduce solder leakage, then the solder protection is improved, but the risk of cracks in metallization layers increases due to thermal stress
Solution Approach 1:
The pull-back distance is segmented into different values across first and second sections of the outer edge, allowing solder leakage protection to be enhanced in specific areas where larger pull-back is applied, while maintaining metallization layer integrity in other areas through optimized smaller pull-back distances.
Solution Approach 2:
Different sections of the substrate are assigned different pull-back distances according to local requirements: sections prone to solder leakage receive larger pull-back for protection, while other sections maintain optimized pull-back distances to preserve metallization layer strength and prevent cracking under thermal stress.
Data Source
Figure 1~2B
Figure 3~4
Figure 5~6
AI summary
A substrate comprises a dielectric insulation layer (11), a first metallization layer (111) arranged on a first surface (101) of the dielectric insulation layer (11), and a second metallization layer (112) arranged on a second surface (102) of the dielectric insulation layer (11), opposite the first surface (101). The dielectric insulation layer (11) comprises an outer edge (113) extending between the first surface (101) and the second surface (102), wherein the outer edge (113) of the dielectric insulation layer (11) comprises a plurality of first sections (A) and a plurality of second sections (B). Along each of the plurality of first sections (A), a difference (diff12) between a first distance (d1) and a second distance (d2) has a first value (v), and along each of the plurality of second sections (B), the difference (diff12) between the first distance (d1) and the second distance (d2) has a second value (w) that is different from the first value (v), wherein the first distance (d1) is a distance between the outer edge (113) of the dielectric insulation layer (11) and an outer edge (1113) of the first metallization layer (111), and the second distance (d2) is a distance between the outer edge (113) of the dielectric insulation layer (11) and an outer edge (1123) of the second metallization layer (112).