Pull-Down Circuit Area Reduction via NMOS Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with pull-down circuits face increased area requirements due to the use of depletion type NMOS transistors or high-resistance elements, which lead to higher consumption currents and larger device sizes.
Innovation Solution
Incorporating both a depletion type NMOS transistor with a gate connected to ground and an enhancement type NMOS transistor with a gate voltage based on the source voltage of the depletion type NMOS transistor, allowing current to flow through channels of both transistors to fix a terminal to ground, reducing the overdrive voltage and transistor sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a depletion type NMOS transistor is used as the pull-down circuit, then the terminal can be fixed to low when power is turned on and when power supply voltage decreases, but the consumption current increases and the area of the pull-down circuit increases
Solution Approach 1:
The pull-down circuit is segmented into two separate NMOS transistors (first NMOS transistor and second NMOS transistor) with different functions. The first NMOS transistor handles the pull-down function when power is turned on, while the second NMOS transistor handles the pull-down function when power supply voltage decreases. This segmentation allows each transistor to be optimized for its specific function, reducing overall consumption current and area compared to using a single depletion type NMOS transistor for both functions.
2Use of energy by stationary object
If the resistance value of the depletion type NMOS transistor is increased to reduce consumption current, then the L length of the transistor increases, but the area of the pull-down circuit increases
Solution Approach 1:
The pull-down function is divided between two NMOS transistors, allowing each transistor to have smaller dimensions. The first NMOS transistor can have a smaller L length because it only needs to handle the power-on pull-down function, and the second NMOS transistor handles the power supply voltage decrease function. This segmentation eliminates the need for a single transistor with high resistance and large L length, thereby reducing the overall area of the pull-down circuit while maintaining low consumption current.
3Use of energy by stationary object
If a high-resistance element is used in place of the depletion type NMOS transistor, then the consumption current is reduced, but the length of the high-resistance element increases and the area of the pull-down circuit increases
Solution Approach 1:
Instead of using a single high-resistance element with large length, the pull-down function is segmented into two NMOS transistors. Each transistor can be designed with smaller dimensions since they share the pull-down function. This segmentation allows achieving low consumption current without requiring a long high-resistance element, thereby reducing the area of the pull-down circuit.
Data Source
AI summary
Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced.