Pull-In Planarization Layer for UBM Adhesion in Semiconductor Packaging

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing semiconductor packaging processes face challenges with delamination between the polymer planarization layer and the passivation layer, which affects the reliability and durability of the redistribution lines and Under-Bump-Metallurgy (UBM) connections.

Innovation Solution

A method and structure where a polymer planarization layer is formed with extensions into the openings of the passivation layer, creating a non-planar interface that acts as an anchor to reduce delamination, and a UBM is formed to extend into these openings for electrical connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If a planarization layer is formed over the passivation layer, then the surface planarity is improved, but delamination occurs between the layers

Engineering Contradiction:
Improvesurface planarityVSAvoidadhesion strength
Core Design Contradiction:
ShapeVSReliability

Solution Approach 1:

The patent transitions from a planar interface to a three-dimensional interlocking interface by forming openings in the passivation layer and extending the planarization layer into these openings. This dimensional change creates mechanical anchoring that prevents delamination while preserving surface planarity where needed.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The planarization layer is nested into the openings of the passivation layer, creating a interlocked structure where one layer is partially contained within the other. This nesting provides mechanical interlocking that enhances adhesion between the layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If the planarization layer is made planar, then subsequent processing is simplified, but electrical connectivity to the metal pad is compromised

Engineering Contradiction:
Improveprocessing simplicityVSAvoidelectrical connectivity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the planarization layer into two functional zones: a planar top surface for simplified processing and a non-planar portion extending into openings for electrical connectivity. This segmentation allows each zone to fulfill its specific function optimally.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The planarization layer exhibits different properties in different locations: it is planar at the top surface for processing ease, but extends into openings at specific locations to provide electrical connectivity. This local differentiation resolves the contradiction between planarity and connectivity.

Inventive Principle:
Principle #3Local quality

3Reliability

If a UBM is formed to connect to the metal pad, then electrical connectivity is improved, but the structure becomes more complex

Engineering Contradiction:
Improveelectrical connectivityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The planarization layer serves multiple functions: it provides surface planarity for processing, acts as a mechanical anchor to prevent delamination, and extends into openings to provide electrical connectivity to the metal pad. This multi-functionality reduces the need for separate dedicated structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the electrical connection function into the planarization layer itself by extending it into the openings to contact the metal pad. This consolidation eliminates the need for a separate connection structure, reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240379428A1Semiconductor structure with pull-in planarization layer and method forming the same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379428A1 patent drawing
  • US20240379428A1 patent drawing
  • US20240379428A1 patent drawing

AI summary

A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.