Pull-Up Transistor Bias Switching for Over-Voltage Tolerant I/O Pads
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Solution Overview
Problem
Existing circuits face issues with over-voltage conditions, leading to I/O pad leakage and latch-up, which can cause device malfunction and communication interruptions, particularly in hot-swap operations and I2C communication scenarios where ICs run at different supply voltages.
Innovation Solution
The implementation of an over-voltage tolerant circuit with a pull-up transistor, sensing circuit, latch, and non-overlap circuit configuration ensures the well of the pull-up transistor is always driven by either Vcc or Vpad, reducing the dead-zone and preventing latch-up, using a non-overlap circuit to ensure the well and gate of the pull-up transistor are substantially always driven by either bias circuit depending on the sensing circuit's output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional hot-swap circuit is used to enable connection during powered operation, then adaptability is improved, but the risk of latch-up and device malfunction increases due to over-voltage conditions
Solution Approach 1:
The circuit proactively drives the n-well to Vcc through transistor P1 before over-voltage conditions occur, establishing a protective bias state in advance. This preliminary action ensures that when hot-swap or over-voltage events occur, the n-well is already properly biased, preventing latch-up while maintaining hot-swap capability
Solution Approach 2:
The n-well node acts as an intermediary element that couples the pull-up PMOS to a controlled voltage source (Vcc) rather than leaving it floating or directly connected to the I/O pad. This intermediary connection provides a stable reference that prevents latch-up during voltage transitions while enabling safe hot-swap operations
2Device complexity
If the n-well of the pull-up PMOS is left floating during voltage transitions, then device complexity is reduced, but communication reliability deteriorates due to interruption risk
Solution Approach 1:
The circuit maintains continuous control of the n-well voltage throughout the entire voltage transition process. Transistor P1 remains active and continuously drives the n-well to Vcc during I/O pad voltage transitions, ensuring that the pull-up PMOS never enters an uncontrolled state. This continuous action prevents communication interruptions while avoiding excessive complexity
3Adaptability or versatility
If I/O pads are connected to powered signals before power supply connection during hot-swap, then adaptability is improved, but harmful over-voltage effects increase
Solution Approach 1:
The circuit applies a counteracting bias to the n-well through transistor P1 that opposes the harmful effects of over-voltage. By proactively establishing a Vcc bias on the n-well, the circuit creates a voltage counter-gradient that prevents excessive voltage differential across the PMOS, thereby protecting against over-voltage damage while enabling hot-swap operations
Data Source
AI summary
Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.