Pulse Address Signal Conversion for Semiconductor Memory Test Mode Generation
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Solution Overview
Problem
Conventional test mode signal generation devices for semiconductor memory apparatuses require a large number of global lines for transmitting test mode signals, leading to complex wiring and reduced layout margins due to the limited number of test mode signals generated from a limited number of address signals.
Innovation Solution
A test mode signal generation device that converts test address signals into pulse signals, which are then transmitted through global lines, allowing for the generation of a greater number of test mode signals while reducing the number of global lines needed by using a pulse address generation unit, a pulse address split unit, and a test mode signal generation unit to produce multiple test mode signals from fewer address signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a limited number of address signals are used to generate test mode signals, then the device complexity is reduced, but the number of generated test mode signals is limited
Solution Approach 1:
The patent applies periodic action by converting address signals into pulse signals that occur at regular intervals. The pulse address generation unit generates periodic pulse signals from the input address signals, and the pulse address split unit distributes these periodic pulses to multiple test mode signal generation units. This periodic pulsing mechanism allows a limited number of address signals to generate a much larger number of test mode signals through temporal multiplication, resolving the contradiction between device complexity and the number of test mode signals.
Solution Approach 2:
The patent introduces a temporal dimension by converting static address signals into time-based pulse signals. Instead of directly using address signals to generate test mode signals in a single dimension, the invention adds the time dimension through pulse generation and splitting. This dimensional transformation allows the system to expand the number of test mode signals from a limited set of address signals by utilizing time-based signal replication and distribution across multiple generation units.
2Ease of operation
If test mode signals are directly transmitted through global lines, then the signal transmission is simple, but the number of global lines increases significantly
Solution Approach 1:
The patent applies segmentation by dividing the test mode signal generation process into multiple independent units. Instead of generating all test mode signals in a single unit and transmitting them through numerous global lines, the invention segments the generation function across multiple test mode signal generation units. Each unit generates a subset of test mode signals locally, reducing the need for a large number of global lines while maintaining simple signal transmission within each segmented unit.
Solution Approach 2:
The patent applies preliminary action by pre-generating and distributing pulse address signals to multiple test mode signal generation units before the actual test mode signal generation occurs. The pulse address generation unit and pulse address split unit perform preliminary processing of the address signals, creating time-synchronized pulse signals that are distributed to various generation units in advance. This preliminary action allows each unit to independently generate test mode signals with fewer global lines required for transmission.
Data Source
AI summary
A test mode signal generation device includes a pulse address generation unit configured to convert test address signals into pulse signals and generate pulse address signals, a pulse address split unit configured to generate converted test address signals in response to the pulse address signals, and a test mode signal generation unit configured to generate a test mode signal in response to the converted test address signals.