Pulse-Biased Memory Power Rail for Stable Voltage Collapse
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Solution Overview
Problem
Conventional memory devices face challenges in providing constant voltage collapse across different rows-per-bitline (RPB) and varying process, voltage, and temperature (PVT) conditions, leading to inefficient area usage and high power consumption during low voltage operations.
Innovation Solution
The implementation of pulsed-biasing power schemes and techniques in memory architecture, which include programmable delay buffering and metal load tracking circuitry, to achieve low power transient-voltage collapse (TVC) with reduced power consumption and constant vddc lowering across RPB, utilizing pulsed-bias inputs to alternately activate transistors and stabilize voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional write assist techniques are used for transient voltage collapse, then low voltage operation is supported, but constant voltage collapse is not provided across different RPB and PVT conditions
Solution Approach 1:
The patent implements dynamic adjustment of write assist parameters based on detected RPB and PVT conditions. The system continuously monitors operational parameters and adjusts voltage collapse characteristics in real-time to maintain consistency across varying conditions, transforming a static write assist approach into a dynamic adaptive system.
Solution Approach 2:
The patent changes key parameters including voltage collapse magnitude, pulse width, and timing based on detected RPB and PVT conditions. By adjusting these parameters dynamically, the system maintains constant voltage collapse characteristics across different operational scenarios, resolving the contradiction between adaptability and reliability.
2Use of energy by stationary object
If known techniques are used for voltage collapse, then low power operation is achieved, but area efficiency is degraded
Solution Approach 1:
The patent implements a universal write assist architecture that serves multiple functions: it provides voltage collapse for low power operation, adapts to different RPB configurations, and compensates for PVT variations. This multi-functional approach eliminates the need for separate circuitry for each function, achieving area efficiency while maintaining low power consumption.
Solution Approach 2:
The system includes self-detection capabilities that automatically identify RPB and PVT conditions and adjust write assist parameters accordingly. This self-service mechanism eliminates the need for external control logic or additional sensing circuitry, reducing area overhead while maintaining optimal power-efficient operation.
3Adaptability or versatility
If conventional techniques generate constant voltage collapse, then voltage consistency is achieved, but large static power is consumed during voltage collapse window
Solution Approach 1:
The patent implements periodic pulsed voltage collapse rather than continuous static voltage collapse. By applying voltage collapse only during necessary write operations in a pulsed manner, the system maintains voltage consistency when needed while dramatically reducing static power consumption during non-operational periods.
Solution Approach 2:
The system rushes through the voltage collapse process by applying it only during the brief window when actually needed for write operations, then immediately returning to normal operation. This skipping approach avoids maintaining constant voltage collapse, thereby eliminating large static power consumption while preserving voltage consistency during critical operations.
Data Source
AI summary
Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.