Pulse Generation Circuit for Adjustable Signal Delay and Noise Cancellation
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Solution Overview
Problem
Conventional signal transfer devices experience variations in signal delay, increased signal delay in multiple transmission-reception systems, and inadequate cancellation of instantaneous transient in-phase noise, which affect their performance in applications like switching power supplies.
Innovation Solution
The proposed solution involves a signal transfer device with a pulse generation circuit that adjusts signal delay, a noise cancel circuit for fast noise cancellation, and a configuration that includes edge detectors, clock generators, frequency dividers, and discharge transistors to manage signal delays and noise effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional signal transfer devices are used, then signal transfer is achieved, but signal delay variation occurs
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the signal delay time in the edge detector block before actual signal transmission. The delay time is calibrated in advance to match the transmission period, ensuring that signal delay variation is minimized from the outset rather than being corrected after the fact.
Solution Approach 2:
The patent changes the delay time parameter in the edge detector block to optimize signal transfer performance. By adjusting the delay time to be equal to or less than the transmission period, the system achieves consistent signal delay across different operating conditions, resolving the contradiction between reliability and time loss.
2Adaptability or versatility
If multiple transmission-reception systems are implemented, then signal transfer capability is improved, but signal delay increases
Solution Approach 1:
The patent segments the signal transfer system into multiple independent transmission-reception channels, each capable of operating autonomously. This segmentation allows parallel signal processing without sequential delays, maintaining low signal delay while supporting multiple simultaneous transmissions and receptions.
Solution Approach 2:
The patent introduces an intermediary mechanism in the edge detector block that synchronizes multiple transmission-reception operations. This intermediary coordinates the timing of different channels, ensuring that signal delay remains consistent across all channels without requiring sequential processing.
3Reliability
If noise cancellation is implemented, then signal quality is improved, but instantaneous transient in-phase noise is not adequately cancelled
Solution Approach 1:
The patent implements feedback mechanisms that monitor the output signals for in-phase noise and adjust the noise cancellation parameters accordingly. The feedback loop detects instantaneous transient noise and dynamically modifies the cancellation strategy, improving the system's ability to handle transient in-phase noise that static cancellation methods miss.
Solution Approach 2:
The patent transitions from static noise cancellation to dynamic noise cancellation by making the cancellation parameters adaptive. The system continuously adjusts its noise cancellation behavior based on real-time signal conditions, enabling it to effectively suppress instantaneous transient in-phase noise while maintaining overall signal quality.
Data Source
AI summary
A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.