Pulse Sending Circuit With Edge Delay for Stable Duty Cycle
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Solution Overview
Problem
Existing pulse signal sending circuits face challenges in maintaining consistent pulse width and duty cycle due to unequal rising and falling lag times, leading to inappropriate signal transmission and increased circuit complexity, which results in larger chip sizes.
Innovation Solution
A pulse signal sending circuit is designed with an output transistor, a CMOS inverter circuit, and a delay circuit that delays the rising or falling of input pulse signals, ensuring equal rising and falling lag times by adjusting the delay time, thus maintaining consistent pulse width and duty cycle, and allowing for accurate slope control of output waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pulse signal sending circuit uses a resistance-load inverter with feedback capacitance to control slopes, then the rising and falling slopes of output waveforms are controlled, but the rising lag time and falling lag time are not equal, causing changes in pulse width and duty cycle
Solution Approach 1:
The patent introduces a preliminary action by adding a delay circuit that pre-adjusts the input signal timing to the inverter circuit. This delay circuit compensates for the inherent asymmetry in rising and falling lag times by intentionally delaying one of the transitions, thereby equalizing the overall lag times and maintaining accurate pulse width and duty cycle in the output signal
Solution Approach 2:
The patent uses a delay circuit as an intermediary element between the input signal source and the inverter circuit. This intermediary component actively manages the timing asymmetry by introducing a controlled delay to balance the rising and falling edges, thus resolving the contradiction between slope control and pulse width accuracy
2Reliability
If a pulse width adjusting circuit is added to maintain accurate pulse width and duty cycle, then the pulse width accuracy is improved, but the circuit scale and chip size are greatly increased
Solution Approach 1:
The patent merges the delay function with the existing inverter circuit structure by using the feedback capacitance and transistor configuration to create an integrated delay mechanism. This combination achieves pulse width maintenance without requiring a completely separate, complex pulse width adjusting circuit, thereby reducing overall circuit scale and chip size
Solution Approach 2:
The patent makes the inverter circuit multi-functional by enabling it to simultaneously perform signal inversion, slope control through feedback capacitance, and pulse width maintenance through the integrated delay mechanism. This universality eliminates the need for separate dedicated circuits for each function, reducing overall device complexity
Data Source
AI summary
A pulse signal sending circuit that outputs pulse signals from an output terminal includes: an output transistor; an inverter circuit; and a delay circuit. The output transistor includes a drain terminal connected to the output terminal. The inverter circuit is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor. The delay circuit receives a pulse signal as an input and delays rising or falling of the input pulse signal. The pulse signal delayed by the delay circuit is input to the inverter circuit.