Pulse Signal Generation Circuit for High-Resolution PWM Timing
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Solution Overview
Problem
Conventional image forming apparatuses face challenges in achieving high-resolution pulse width modulation (PWM) signals due to propagation delays in counter circuits, which hinder the increase in scanning speed and resolution required for accurate shading correction and motor control.
Innovation Solution
A pulse signal generation circuit is implemented, separating the PWM signal generation into a region operating in synchronization with a low-speed clock and a shift register operating in synchronization with a high-speed clock, using a pattern generation unit to generate bit patterns and a clock signal generation unit to synchronize the output, thereby reducing data propagation delays and increasing PWM resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock speed is increased to improve PWM output resolution and responsiveness, then the PWM output resolution and responsiveness are improved, but data propagation delays in counter circuits increase causing failure to update data in time
Solution Approach 1:
The patent divides the PWM signal generation into two independent modules: a low-speed clock module for counter calculations and a high-speed clock module for pattern output. This segmentation allows each module to operate at its optimal speed without interference, resolving the contradiction between high-speed output and reliable data updates by eliminating propagation delays in the counter circuit.
Solution Approach 2:
The patent introduces a pattern generation unit as an intermediary that converts counter values into PWM patterns. This intermediary module acts as a buffer between the low-speed counter and the high-speed output, allowing the counter to update reliably at low speed while the pattern output occurs at high speed, thus resolving the timing conflict.
2Speed
If the clock speed is increased to improve responsiveness, then the responsiveness is improved, but propagation delays cause incorrect PWM signal generation
Solution Approach 1:
The patent segments the clock system into two independent clock domains: a low-speed clock for reliable counter operations and a high-speed clock for rapid pattern output. This segmentation enables the system to achieve high responsiveness through the high-speed clock while maintaining signal precision through the low-speed counter operations, eliminating the trade-off between speed and precision.
3Device complexity
If a single high-speed clock is used for both counter calculations and pattern output, then the system complexity is reduced, but data propagation delays increase causing update failures
Solution Approach 1:
The patent divides the clock system into two independent clock modules operating at different speeds. This segmentation, while slightly increasing system complexity, ensures reliable data updates by preventing propagation delays that would occur in a single high-speed clock system, thus prioritizing reliability over minimal complexity.
Solution Approach 2:
The patent changes the clock speed parameter for different functional modules: the counter module operates at a low clock speed to ensure reliable updates, while the pattern output module operates at a high clock speed for responsiveness. This parameter differentiation resolves the contradiction between simplicity and reliability.
Data Source
AI summary
There is provided a pulse signal generation circuit capable of generating a high-resolution pulse signal by generating pattern data by performing a logical operation on rising data that indicates the rising of a pulse signal and falling data that indicates the falling of the pulse signal.