Pulse-Based Clock Generation for Fast Synchronization Without PLLs
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Solution Overview
Problem
Existing clock synchronization methods for high-speed data transmission interfaces like USB and PCIe are inefficient due to requirements for input reference clocks, lengthy synchronization times, and the need for external oscillators, which can lead to synchronization failures and increased production costs.
Innovation Solution
A clock generation method and system that utilizes pulse recognition techniques to quickly synchronize clocks through a digital-to-analog converter and oscillator, eliminating the need for additional crystal or ceramic oscillators, and includes temperature, feedback, and power noise compensation to enhance stability and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase lock loop (PLL) or delay lock loop (DLL) techniques are used for clock synchronization, then clock synchronization can be achieved, but the synchronization time is extended and the circuit complexity increases
Solution Approach 1:
The patent extracts only the essential function of clock synchronization from the complex PLL/DLL systems. By using a simple counter to detect clock cycles and calculate frequency directly from the received signal, it eliminates the need for complex phase locking circuits while achieving the same synchronization goal.
Solution Approach 2:
The patent replaces the mechanical/complex circuit-based PLL/DLL systems with a software/algorithm-based approach. The frequency detection and clock generation are achieved through digital counting and calculation methods rather than analog circuitry, reducing hardware complexity and synchronization time.
2Reliability
If phase lock loop (PLL) or delay lock loop (DLL) techniques are used for clock synchronization, then clock synchronization can be achieved, but the circuit complexity increases
Solution Approach 1:
The patent extracts only the essential function of clock synchronization from the complex PLL/DLL systems. By using a simple counter to detect clock cycles and calculate frequency directly from the received signal, it eliminates the need for complex phase locking circuits while achieving the same synchronization goal.
Solution Approach 2:
The patent replaces the mechanical/complex circuit-based PLL/DLL systems with a software/algorithm-based approach. The frequency detection and clock generation are achieved through digital counting and calculation methods rather than analog circuitry, reducing hardware complexity and synchronization time.
3Reliability
If external crystal or ceramic oscillator is used for clock generation, then clock pulses can be generated, but the production cost increases
Solution Approach 1:
The patent enables the receiving device to generate its own clock signal from the received data signal itself. By detecting the frequency of incoming clock cycles and using a local oscillator controlled by the calculated frequency, the system eliminates the need for external crystal or ceramic oscillators, reducing component count and production cost.
Solution Approach 2:
The local oscillator serves multiple functions: it generates the clock signal for data reception and its frequency is dynamically adjusted based on the detected signal frequency. This multi-functional approach replaces the need for dedicated external oscillators while maintaining clock generation reliability.
Data Source
AI summary
The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.