Pulse-Based Clock Gating Without Latch Setup Delay
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Solution Overview
Problem
Existing clock-gating circuits in digital electronic systems face performance limitations due to longer setup times and clock-to-output delays, which affect processor performance by increasing clock cycle periods.
Innovation Solution
A high-performance clock-gating circuit is implemented using a pulse-based design, incorporating a first pull-down stack, an inverter, and pull-up stacks with shadow latches to manage the enable and clock signals efficiently, reducing delays and maintaining output states during pulse events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a typical clock-gating circuit uses a latch followed by an AND-gate, then the circuit can control clock signal propagation, but the performance is limited by enable-to-clock setup time and clock-to-Q propagation delay
Solution Approach 1:
The patent extracts the latch component from the traditional clock-gating circuit architecture, removing the source of setup time delays. By eliminating the latch and using only combinational logic (AND-gate or transmission gate) to control clock propagation, the circuit achieves faster response without the sequential element delay penalties.
Solution Approach 2:
The patent segments the clock-gating function into separate controllable paths using enable signals that directly control AND-gates or transmission gates. This segmentation allows independent optimization of each clock path without being constrained by a centralized latch's setup time requirements.
2Reliability
If the clock cycle period is determined by processing time between flip-flops, then data can be processed correctly, but the period increases based on setup time and clock-to-output delay
Solution Approach 1:
The patent applies preliminary action by pre-positioning enable signals to control clock gating before the actual data processing occurs. The enable signals are prepared in advance and directly control the clock propagation paths, ensuring that clock signals are already optimally routed when data processing begins, thus minimizing the required clock cycle period while maintaining reliability.
3Stability of the object's composition
If a clock-gating circuit includes a latch to register the enable signal, then the enable signal can be synchronized, but the latch setup time dictates the overall circuit performance
Solution Approach 1:
The patent substitutes the mechanical/sequential latch system with a combinational logic system. Instead of using a latch that requires setup time and has inherent delay characteristics, the circuit uses enable signals that directly control AND-gates or transmission gates through combinational logic, eliminating the sequential element and achieving faster response speeds while maintaining signal synchronization through logical control.
Data Source
AI summary
Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.