Pulse-Based Multi-Wire Clock Recovery Without Separate Clock Lanes
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Solution Overview
Problem
Current communication systems face challenges in providing flexible and reliable clock and data recovery in multi-wire interfaces that employ pulse-based signaling, particularly in complex signaling environments where clock and data signals are prone to skew and require separate lanes, leading to increased device pin count and semiconductor real estate usage.
Innovation Solution
A clock recovery circuit and method that embeds clock information within data signals using pulse-based encoding, allowing for reliable clock generation and data decoding by transcoding data into multi-digit numbers expressed in base (2N−1) or ternary/septenary formats, eliminating the need for separate clock channels and phase-locked loops, and supporting capacitively, inductively, or optically coupled interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock channels and phase-locked loops are used for clock and data recovery, then clock and data signals can be recovered reliably, but device pin count and semiconductor real estate increase
Solution Approach 1:
The patent combines clock and data signals into a single multi-wire interface by encoding clock information within data signals using pulse-based signaling. Multiple wires carry combined clock and data information, eliminating the need for separate clock channels and reducing device pin count while maintaining recovery reliability through the structured pulse encoding scheme
Solution Approach 2:
The multi-wire interface serves multiple functions simultaneously: it carries both clock and data signals, provides skew compensation through differential timing, and enables error detection. Each wire acts as a universal carrier that can transmit clock information, data information, or both, depending on the signaling mode employed
2Reliability
If separate clock lanes are used, then clock and data signals can be transmitted independently, but the number of interconnects increases
Solution Approach 1:
The patent merges clock and data transmission into the same physical interconnects by using pulse-based encoding where clock edges trigger data capture. The same wires that carry data also carry implicit clock information through the timing and structure of pulse transitions, thereby reducing the total number of interconnects required
3Device complexity
If pulse-based encoding is used to embed clock information, then separate clock channels are eliminated, but skew between clock and data signals must be minimized
Solution Approach 1:
The patent segments the transmission into multiple wires where skew between wires can be measured and compensated. By dividing the data stream across multiple channels and using reference pulses on each wire, the system can identify and correct timing differences between wires, managing skew requirements through structured segmentation rather than requiring absolute precision across all signals
Data Source
AI summary
A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.